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update reports & add mlkem cdc test result & update pll

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FallenSigh
2026-07-11 10:09:45 +08:00
parent e30a65bd72
commit 4857016b42
36 changed files with 162316 additions and 131146 deletions
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183
fpga/vivado_reports_nodsp/power.rpt
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@@ -1,16 +1,20 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
| Date : Wed Jul 8 03:34:25 2026
<<<<<<< Updated upstream
| Date : Fri Jul 10 04:15:05 2026
=======
| Date : Sat Jul 11 09:21:02 2026
>>>>>>> Stashed changes
| Host : fedora running 64-bit unknown
| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt
| Command : report_power -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/power.rpt
| Design : soc_top
| Device : xc7a200tfbg676-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------
Power Report
@@ -30,14 +34,25 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.549 |
<<<<<<< Updated upstream
| Total On-Chip Power (W) | 0.686 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.409 |
| Dynamic (W) | 0.545 |
| Device Static (W) | 0.141 |
| Effective TJA (C/W) | 1.9 |
| Max Ambient (C) | 84.0 |
| Junction Temperature (C) | 26.0 |
| Max Ambient (C) | 83.7 |
| Junction Temperature (C) | 26.3 |
=======
| Total On-Chip Power (W) | 0.779 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.637 |
| Device Static (W) | 0.142 |
| Effective TJA (C/W) | 1.9 |
| Max Ambient (C) | 83.5 |
| Junction Temperature (C) | 26.5 |
>>>>>>> Stashed changes
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -52,22 +67,39 @@ Table of Contents
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.042 | 7 | --- | --- |
| Slice Logic | 0.069 | 120086 | --- | --- |
| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 |
| CARRY4 | 0.002 | 2859 | 33450 | 8.55 |
| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 |
| Register | <0.001 | 39931 | 267600 | 14.92 |
<<<<<<< Updated upstream
| Clocks | 0.056 | 6 | --- | --- |
| Slice Logic | 0.109 | 133224 | --- | --- |
| LUT as Logic | 0.102 | 75460 | 133800 | 56.40 |
| CARRY4 | 0.003 | 3546 | 33450 | 10.60 |
| LUT as Distributed RAM | 0.002 | 628 | 46200 | 1.36 |
| Register | 0.001 | 39690 | 267600 | 14.83 |
| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 |
| Others | 0.000 | 318 | --- | --- |
| Signals | 0.115 | 85084 | --- | --- |
| Block RAM | 0.019 | 23.5 | 365 | 6.44 |
| PLL | 0.132 | 1 | 10 | 10.00 |
| DSPs | 0.009 | 16 | 740 | 2.16 |
| I/O | 0.023 | 202 | 400 | 50.50 |
| F7/F8 Muxes | <0.001 | 6085 | 133800 | 4.55 |
| Others | 0.000 | 289 | --- | --- |
| Signals | 0.194 | 93202 | --- | --- |
| Block RAM | 0.019 | 25.5 | 365 | 6.99 |
| PLL | 0.137 | 1 | 10 | 10.00 |
| I/O | 0.029 | 202 | 400 | 50.50 |
| Static Power | 0.141 | | | |
| Total | 0.549 | | | |
| Total | 0.686 | | | |
=======
| Clocks | 0.060 | 7 | --- | --- |
| Slice Logic | 0.137 | 103629 | --- | --- |
| LUT as Logic | 0.128 | 53158 | 133800 | 39.73 |
| CARRY4 | 0.005 | 3669 | 33450 | 10.97 |
| Register | 0.002 | 31000 | 267600 | 11.58 |
| LUT as Distributed RAM | 0.001 | 740 | 46200 | 1.60 |
| LUT as Shift Register | <0.001 | 1168 | 46200 | 2.53 |
| F7/F8 Muxes | <0.001 | 2449 | 133800 | 1.83 |
| Others | 0.000 | 333 | --- | --- |
| Signals | 0.284 | 78815 | --- | --- |
| Block RAM | 0.027 | 29.5 | 365 | 8.08 |
| PLL | 0.102 | 1 | 10 | 10.00 |
| I/O | 0.027 | 202 | 400 | 50.50 |
| Static Power | 0.142 | | | |
| Total | 0.779 | | | |
>>>>>>> Stashed changes
+--------------------------+-----------+----------+-----------+-----------------+
@@ -77,16 +109,21 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 0.294 | 0.262 | 0.032 |
| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 |
| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 |
<<<<<<< Updated upstream
| Vccint | 1.000 | 0.423 | 0.391 | 0.032 |
| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 |
=======
| Vccint | 1.000 | 0.545 | 0.512 | 0.033 |
| Vccaux | 1.800 | 0.085 | 0.054 | 0.031 |
>>>>>>> Stashed changes
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 |
| Vccbram | 1.000 | 0.003 | 0.002 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
@@ -130,15 +167,26 @@ Table of Contents
2.2 Clock Constraints
---------------------
+-------------------+------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------------------+------------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+-------------------+------------------------------------------+-----------------+
<<<<<<< Updated upstream
+------------------+-----------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------------+-----------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+------------------+-----------------------------------------+-----------------+
=======
+------------------+------------------------------------------+-----------------+
| Clock | Domain | Constraint (ns) |
+------------------+------------------------------------------+-----------------+
| clk | clk | 20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.0 |
| mlkem_clk | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 13.0 |
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
+------------------+------------------------------------------+-----------------+
>>>>>>> Stashed changes
3. Detailed Reports
@@ -150,31 +198,64 @@ Table of Contents
+----------------------------+-----------+
| Name | Power (W) |
+----------------------------+-----------+
| soc_top | 0.409 |
| pll_clk.u_clk_pll | 0.133 |
| inst | 0.133 |
<<<<<<< Updated upstream
| soc_top | 0.545 |
| pll_clk.u_clk_pll | 0.138 |
| inst | 0.138 |
| u_Axi_CDC | 0.003 |
| u_axi_uart_controller | 0.002 |
| u_cpu | 0.025 |
| addr_trans | 0.002 |
| tlb_entry | 0.002 |
| btb | 0.003 |
| dcache | 0.006 |
| icache | 0.005 |
| u_csr | 0.001 |
| u_mul | 0.004 |
| u_fft_mlkem_axi_slave | 0.251 |
| u_fft_controller | 0.030 |
| u_FFT | 0.027 |
| u_out0 | 0.001 |
| u_out1 | 0.001 |
| u_mlkem_axi_slave | 0.221 |
| u_mlkem | 0.218 |
| u_matmul_axi_slave | 0.081 |
=======
| soc_top | 0.637 |
| pll_clk.u_clk_pll | 0.103 |
| inst | 0.103 |
| u_Axi_CDC | 0.002 |
| u_axi_uart_controller | 0.001 |
| u_axi_uart_controller | 0.002 |
| uart0 | 0.001 |
| regs | 0.001 |
| u_cdma_matmul_bridge | 0.001 |
| u_cpu | 0.018 |
| u_confreg | 0.001 |
| u_cpu | 0.027 |
| addr_trans | 0.002 |
| tlb_entry | 0.002 |
| btb | 0.002 |
| btb | 0.003 |
| dcache | 0.004 |
| icache | 0.005 |
| u_csr | 0.002 |
| u_fft_mlkem_axi_slave | 0.148 |
| u_fft_controller | 0.032 |
| u_FFT | 0.029 |
| u_mlkem_axi_cdc | 0.002 |
| u_mlkem_axi_slave | 0.115 |
| u_mlkem | 0.113 |
| u_matmul_axi_slave | 0.065 |
| u_snix_axil_cdma_mux_8ch | 0.009 |
| u_csr | 0.001 |
| u_mul | 0.008 |
| u_fft_mlkem_axi_slave | 0.373 |
| u_fft_controller | 0.031 |
| u_FFT | 0.028 |
| u_out0 | 0.001 |
| u_out1 | 0.001 |
| u_mlkem_axi_cdc | 0.003 |
| wFifo | 0.001 |
| u_mlkem_axi_slave | 0.339 |
| u_mlkem | 0.332 |
| u_matmul_axi_slave | 0.077 |
>>>>>>> Stashed changes
| mult_inst[0].u_mult | 0.003 |
| mult_inst[1].u_mult | 0.002 |
| mult_inst[2].u_mult | 0.002 |
| mult_inst[3].u_mult | 0.002 |
| u_snix_axil_cdma_mux_8ch | 0.008 |
| u_core_engine | 0.004 |
| axis_fifo_u0 | 0.003 |
| axis_fifo_u0 | 0.002 |
+----------------------------+-----------+