update reports & add mlkem cdc test result & update pll
This commit is contained in:
@@ -1,14 +1,18 @@
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 03:34:05 2026
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<<<<<<< Updated upstream
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| Date : Fri Jul 10 04:14:46 2026
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=======
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| Date : Sat Jul 11 09:20:51 2026
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>>>>>>> Stashed changes
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| Host : fedora running 64-bit unknown
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| Command : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt
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| Command : report_methodology -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/methodology.rpt
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| Design : soc_top
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| Device : xc7a200tfbg676-1
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| Speed File : -1
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| Design State : Fully Routed
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------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------------------------------
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Report Methodology
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@@ -23,17 +27,27 @@ Table of Contents
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Floorplan: impl_1
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Design limits: <entire design considered>
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Max violations: <unlimited>
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Violations found: 99
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<<<<<<< Updated upstream
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Violations found: 107
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=======
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Violations found: 115
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>>>>>>> Stashed changes
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+-----------+----------+-------------------------------------------------------------------+------------+
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| Rule | Severity | Description | Violations |
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+-----------+----------+-------------------------------------------------------------------+------------+
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| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
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| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 |
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| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 1 |
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<<<<<<< Updated upstream
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| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 9 |
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| SYNTH-16 | Warning | Address collision | 8 |
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=======
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| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 6 |
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| SYNTH-16 | Warning | Address collision | 16 |
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| TIMING-9 | Warning | Unknown CDC Logic | 1 |
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>>>>>>> Stashed changes
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| TIMING-10 | Warning | Missing property on synchronizer | 1 |
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| TIMING-18 | Warning | Missing input or output delay | 76 |
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| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 2 |
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| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 4 |
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| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 |
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| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 |
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+-----------+----------+-------------------------------------------------------------------+------------+
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@@ -42,7 +56,11 @@ Table of Contents
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-----------------
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LUTAR-1#1 Warning
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LUT drives async reset alert
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LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
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<<<<<<< Updated upstream
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LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24656 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
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=======
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LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 15633 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-5#1 Warning
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@@ -87,7 +105,71 @@ Related violations: <none>
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SYNTH-6#1 Warning
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Timing of a block RAM might be sub-optimal
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The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#2 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#3 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#4 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#5 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#6 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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Related violations: <none>
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SYNTH-6#7 Warning
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Timing of a block RAM might be sub-optimal
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The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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Related violations: <none>
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SYNTH-6#8 Warning
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Timing of a block RAM might be sub-optimal
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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Related violations: <none>
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SYNTH-6#9 Warning
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Timing of a block RAM might be sub-optimal
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-16#1 Warning
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@@ -130,6 +212,51 @@ Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#9 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#10 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#11 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#12 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#13 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#14 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#15 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#16 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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TIMING-9#1 Warning
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Unknown CDC Logic
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One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities
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Related violations: <none>
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TIMING-10#1 Warning
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Missing property on synchronizer
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One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
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@@ -517,12 +644,22 @@ Related violations: <none>
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TIMING-47#1 Warning
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False path or asynchronous clock group between synchronous clocks
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A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
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A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
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Related violations: <none>
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TIMING-47#2 Warning
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False path or asynchronous clock group between synchronous clocks
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A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
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A Clock Group timing constraint is set between synchronous clocks mlkem_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
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Related violations: <none>
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TIMING-47#3 Warning
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False path or asynchronous clock group between synchronous clocks
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A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
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Related violations: <none>
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TIMING-47#4 Warning
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False path or asynchronous clock group between synchronous clocks
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A Clock Group timing constraint is set between synchronous clocks sys_clk and mlkem_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
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Related violations: <none>
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XDCC-1#1 Warning
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