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update reports & add mlkem cdc test result & update pll

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FallenSigh
2026-07-11 10:09:45 +08:00
parent e30a65bd72
commit 4857016b42
36 changed files with 162316 additions and 131146 deletions
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15
fpga/constraints/soc.xdc
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@@ -227,10 +227,19 @@ set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
# create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
# create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk]
# set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk]
create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]
create_generated_clock -name mlkem_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2]
set_clock_groups -asynchronous \
-group [get_clocks cpu_clk] \
-group [get_clocks sys_clk] \
-group [get_clocks mlkem_clk]
set_input_delay -clock sys_clk -max 3 [get_ports {base_ram_data[*]}]
set_input_delay -clock sys_clk -min 2 [get_ports {base_ram_data[*]}]