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fix: change <= to = in array for loops for verilator BLKLOOPINIT

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FallenSigh
2026-06-30 02:15:14 +08:00
parent 99e6c884d7
commit 3617ee7656
3 changed files with 6 additions and 6 deletions
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2
rtl/ip/mlkem/ntt/ntt_core.v
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@@ -74,7 +74,7 @@ module ntt_core (
if (!rst_n) begin if (!rst_n) begin
state<=S_IDLE; load_cnt<=0; out_cnt<=0; j<=0; start<=0; layer_len<=0; state<=S_IDLE; load_cnt<=0; out_cnt<=0; j<=0; start<=0; layer_len<=0;
zeta_idx<=0; layer<=0; bf_done<=0; r_a<=0; r_b<=0; r_wa<=0; r_wb<=0; zeta_idx<=0; layer<=0; bf_done<=0; r_a<=0; r_b<=0; r_wa<=0; r_wb<=0;
for (ci=0; ci<N; ci=ci+1) cr[ci] <= 0; for (ci=0; ci<N; ci=ci+1) cr[ci] = 0;
end else begin end else begin
state <= next_state; state <= next_state;

4
rtl/ip/mlkem/poly_mul/poly_mul_sync.v
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@@ -117,8 +117,8 @@ module poly_mul_sync (
c0_reg <= 12'd0; c0_reg <= 12'd0;
c1_reg <= 12'd0; c1_reg <= 12'd0;
for (i = 0; i < 256; i = i + 1) begin for (i = 0; i < 256; i = i + 1) begin
mem_A[i] <= 12'd0; mem_A[i] = 12'd0;
mem_B[i] <= 12'd0; mem_B[i] = 12'd0;
end end
end else begin end else begin
state <= next_state; state <= next_state;

6
rtl/ip/mlkem/top/mlkem_axi_slave.v
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@@ -340,9 +340,9 @@ module mlkem_axi_slave (
pre_byte_l <= 8'd0; pre_byte_l <= 8'd0;
w_last_l <= 1'b0; w_last_l <= 1'b0;
for (wi = 0; wi < 8; wi = wi + 1) begin for (wi = 0; wi < 8; wi = wi + 1) begin
d_word[wi] <= 32'd0; d_word[wi] = 32'd0;
z_word[wi] <= 32'd0; z_word[wi] = 32'd0;
msg_word[wi] <= 32'd0; msg_word[wi] = 32'd0;
end end
end else begin end else begin
// clear the preload-busy flag when the mlkem domain acks the byte // clear the preload-busy flag when the mlkem domain acks the byte