fix: change <= to = in array for loops for verilator BLKLOOPINIT

2026-06-30 02:15:14 +08:00
parent 99e6c884d7
commit 3617ee7656
3 changed files with 6 additions and 6 deletions
--- a/rtl/ip/mlkem/poly_mul/poly_mul_sync.v
+++ b/rtl/ip/mlkem/poly_mul/poly_mul_sync.v
@@ -117,8 +117,8 @@ module poly_mul_sync (
            c0_reg   <= 12'd0;
            c1_reg   <= 12'd0;
            for (i = 0; i < 256; i = i + 1) begin
-                mem_A[i] <= 12'd0;
-                mem_B[i] <= 12'd0;
+                mem_A[i] = 12'd0;
+                mem_B[i] = 12'd0;
            end
        end else begin
            state <= next_state;