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Optimize CDMA matmul bridge scheduling

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FallenSigh
2026-07-04 19:59:49 +08:00
parent c37f493bcb
commit 27cdfb713a
3 changed files with 106 additions and 40 deletions
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67
rtl/ip/matmul/matmul_axi_slave.v
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@@ -582,14 +582,39 @@ module matmul_axi_slave (
// Pipeline delay shift registers for accumulation (4 stages = 3 multiplier pipe + 1)
reg [3:0] acc_idx_d1, acc_idx_d2, acc_idx_d3, acc_idx_d4;
reg acc_bank_d1, acc_bank_d2, acc_bank_d3, acc_bank_d4;
reg acc_valid_d1, acc_valid_d2, acc_valid_d3, acc_valid_d4;
reg [4:0] pipe_cnt;
wire [65:0] calc_c_result = ({2'b0, mult_p[0]} + {2'b0, mult_p[1]}) +
({2'b0, mult_p[2]} + {2'b0, mult_p[3]});
wire calc_crc_valid = (state == C_RUN) && (pipe_cnt >= 5'd4) && (pipe_cnt < 5'd20);
wire calc_crc_valid = acc_valid_d4;
wire [31:0] crc_calc_0 = crc32_word_next(crc_reg, calc_c_result[31:0]);
wire [31:0] crc_calc_1 = crc32_word_next(crc_calc_0, calc_c_result[63:32]);
wire [31:0] crc_calc_2 = crc32_word_next(crc_calc_1, {30'b0, calc_c_result[65:64]});
task start_calc_bank;
input bank;
begin
cur_bank <= bank;
busy <= 1'b1;
state <= C_RUN;
pipe_cnt <= 5'd1;
acc_idx_d1 <= 4'd0;
acc_bank_d1 <= bank;
acc_valid_d1 <= 1'b1;
if (bank == 1'b0) begin
m_in_a[0] <= b0_a[4'd0]; m_in_b[0] <= b0_b[4'd0];
m_in_a[1] <= b0_a[4'd1]; m_in_b[1] <= b0_b[4'd4];
m_in_a[2] <= b0_a[4'd2]; m_in_b[2] <= b0_b[4'd8];
m_in_a[3] <= b0_a[4'd3]; m_in_b[3] <= b0_b[4'd12];
end else begin
m_in_a[0] <= b1_a[4'd0]; m_in_b[0] <= b1_b[4'd0];
m_in_a[1] <= b1_a[4'd1]; m_in_b[1] <= b1_b[4'd4];
m_in_a[2] <= b1_a[4'd2]; m_in_b[2] <= b1_b[4'd8];
m_in_a[3] <= b1_a[4'd3]; m_in_b[3] <= b1_b[4'd12];
end
end
endtask
// CRC tracks completed C elements directly, independent of result writeback.
always @(posedge clk) begin
if (!resetn) begin
@@ -616,6 +641,10 @@ module matmul_axi_slave (
acc_bank_d2 <= 1'b0;
acc_bank_d3 <= 1'b0;
acc_bank_d4 <= 1'b0;
acc_valid_d1 <= 1'b0;
acc_valid_d2 <= 1'b0;
acc_valid_d3 <= 1'b0;
acc_valid_d4 <= 1'b0;
end else begin
calc_done_pulse <= 1'b0;
@@ -623,24 +652,24 @@ module matmul_axi_slave (
acc_idx_d4 <= acc_idx_d3;
acc_idx_d3 <= acc_idx_d2;
acc_idx_d2 <= acc_idx_d1;
acc_idx_d1 <= pipe_cnt[3:0];
acc_idx_d1 <= 4'd0;
acc_bank_d4 <= acc_bank_d3;
acc_bank_d3 <= acc_bank_d2;
acc_bank_d2 <= acc_bank_d1;
acc_bank_d1 <= cur_bank;
acc_bank_d1 <= 1'b0;
acc_valid_d4 <= acc_valid_d3;
acc_valid_d3 <= acc_valid_d2;
acc_valid_d2 <= acc_valid_d1;
acc_valid_d1 <= 1'b0;
case (state)
C_IDLE: begin
pipe_cnt <= 5'd0;
if (req_0) begin
cur_bank <= 1'b0;
busy <= 1'b1;
state <= C_RUN;
start_calc_bank(1'b0);
end else if (req_1) begin
cur_bank <= 1'b1;
busy <= 1'b1;
state <= C_RUN;
start_calc_bank(1'b1);
end else begin
pipe_cnt <= 5'd0;
busy <= 1'b0;
end
end
@@ -648,6 +677,9 @@ module matmul_axi_slave (
C_RUN: begin
// Issue 4 new operands every cycle (pipe_cnt 0-15, 16 rounds)
if (pipe_cnt < 5'd16) begin
acc_idx_d1 <= pipe_cnt[3:0];
acc_bank_d1 <= cur_bank;
acc_valid_d1 <= 1'b1;
if (cur_bank == 1'b0) begin
m_in_a[0] <= b0_a[{pipe_cnt[3:2], 2'd0}]; m_in_b[0] <= b0_b[{2'd0, pipe_cnt[1:0]}];
m_in_a[1] <= b0_a[{pipe_cnt[3:2], 2'd1}]; m_in_b[1] <= b0_b[{2'd1, pipe_cnt[1:0]}];
@@ -661,16 +693,25 @@ module matmul_axi_slave (
end
end
// Accumulate results from 4 cycles ago (pipe_cnt 4-19)
if (pipe_cnt >= 5'd4 && pipe_cnt < 5'd20) begin
// Accumulate results from 4 cycles ago.
if (acc_valid_d4) begin
if (acc_bank_d4 == 1'b0)
b0_c[acc_idx_d4] <= calc_c_result;
else
b1_c[acc_idx_d4] <= calc_c_result;
end
if (pipe_cnt == 5'd20) begin
if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
calc_done_pulse <= 1'b1;
end
if (pipe_cnt < 5'd16) begin
pipe_cnt <= pipe_cnt + 5'd1;
end else if (cur_bank == 1'b0 && req_1) begin
start_calc_bank(1'b1);
end else if (cur_bank == 1'b1 && req_0) begin
start_calc_bank(1'b0);
end else if (acc_valid_d4 && acc_idx_d4 == 4'd15) begin
busy <= 1'b0;
state <= C_IDLE;
end else begin