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Optimize CDMA matmul bridge scheduling

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FallenSigh
2026-07-04 19:59:49 +08:00
parent c37f493bcb
commit 27cdfb713a
3 changed files with 106 additions and 40 deletions
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38
rtl/ip/cdma/cdma_matmul_bridge.sv
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@@ -103,6 +103,9 @@ module cdma_matmul_bridge #(
logic [31:0] seq_store_idx;
logic seq_compute_bank;
logic seq_skip_writeback;
logic seq_defer_load_start;
logic seq_deferred_start_valid;
logic seq_deferred_start_bank;
wire [7:0] wr_off = s_axil_awaddr[7:0];
wire [7:0] rd_off = s_axil_araddr[7:0];
@@ -223,6 +226,9 @@ module cdma_matmul_bridge #(
seq_store_idx <= 32'd0;
seq_compute_bank <= 1'b0;
seq_skip_writeback <= 1'b0;
seq_defer_load_start <= 1'b0;
seq_deferred_start_valid <= 1'b0;
seq_deferred_start_bank <= 1'b0;
cdma_req_valid <= 1'b0;
cdma_req_mode <= MODE_MEM2EP;
cdma_req_src <= '0;
@@ -254,6 +260,9 @@ module cdma_matmul_bridge #(
seq_store_idx <= 32'd0;
seq_compute_bank <= 1'b0;
seq_skip_writeback <= s_axil_wstrb[0] && s_axil_wdata[1];
seq_defer_load_start <= 1'b0;
seq_deferred_start_valid <= 1'b0;
seq_deferred_start_bank <= 1'b0;
mat_crc_clear <= 1'b1;
mat_done_clear <= 1'b1;
seq_state <= SQ_CLEAR;
@@ -285,13 +294,20 @@ module cdma_matmul_bridge #(
SQ_LOAD_WAIT: begin
if (cdma_req_done) begin
mat_start_valid <= 1'b1;
mat_start_bank <= cdma_req_ep_bank[0];
seq_load_idx <= seq_load_idx + 32'd1;
if ((seq_load_idx + 32'd1) < seq_groups && (seq_load_idx == 32'd0)) begin
seq_state <= SQ_LOAD_START;
seq_load_idx <= seq_load_idx + 32'd1;
if (seq_defer_load_start) begin
seq_defer_load_start <= 1'b0;
seq_deferred_start_valid <= 1'b1;
seq_deferred_start_bank <= cdma_req_ep_bank[0];
seq_state <= SQ_STORE_START;
end else begin
seq_state <= SQ_WAIT_DONE;
mat_start_valid <= 1'b1;
mat_start_bank <= cdma_req_ep_bank[0];
if ((seq_load_idx + 32'd1) < seq_groups && (seq_load_idx == 32'd0)) begin
seq_state <= SQ_LOAD_START;
end else begin
seq_state <= SQ_WAIT_DONE;
end
end
end
end
@@ -309,6 +325,9 @@ module cdma_matmul_bridge #(
end else begin
seq_state <= SQ_WAIT_DONE;
end
end else if (seq_load_idx < seq_groups) begin
seq_defer_load_start <= 1'b1;
seq_state <= SQ_LOAD_START;
end else begin
seq_state <= SQ_STORE_START;
end
@@ -338,10 +357,15 @@ module cdma_matmul_bridge #(
if (cdma_req_done) begin
seq_store_idx <= seq_store_idx + 32'd1;
seq_compute_bank <= ~seq_compute_bank;
if (seq_deferred_start_valid) begin
mat_start_valid <= 1'b1;
mat_start_bank <= seq_deferred_start_bank;
seq_deferred_start_valid <= 1'b0;
end
if ((seq_store_idx + 32'd1) >= seq_groups) begin
seq_state <= SQ_DONE;
end else if (seq_load_idx < seq_groups) begin
seq_state <= SQ_LOAD_START;
seq_state <= SQ_WAIT_DONE;
end else begin
seq_state <= SQ_WAIT_DONE;
end