FallenSigh
9824ed8f2c
Add ST_H stage: second sha3_top (mb_en=1) computes H(ek) over 800B ek as 6 pre-padded SHA3-256 rate blocks. Per block: assemble 136 bytes (h_padbyte applies 0x06...0x80 padding on final block) into h_block_r, feed (hold valid until mb_ready drops), wait permute; capture digest on last block into hek_r. Full dk readback tap: dk = dk_pke(768) || ek(800) || H(ek)(32) || z(32) = 1632B. End-to-end TB (tb_mlkem_kg_kat_xsim, no force/release): drive KAT count=0 d/z, run full KeyGen FSM (IDLE->G->A->C->N->M->E->H->DONE), verify: ek == KAT pk (800B) byte-exact dk == KAT sk (1632B) byte-exact Done in 21403 cycles. ML-KEM-512 KeyGen complete and KAT-verified. Prior stage TBs (2c/2e/2f) still pass (no regression).
69 lines
3.0 KiB
Verilog
69 lines
3.0 KiB
Verilog
// tb_mlkem_kg_kat_xsim.v - Stage 4 end-to-end: full ML-KEM-512 KeyGen vs NIST KAT.
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// Drives d/z (KAT count=0), runs KeyGen, verifies:
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// ek (800B, sel=0) == KAT pk
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// dk (1632B, dk tap) == KAT sk (= dk_pke || ek || H(ek) || z)
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// No force/release — pure valid/ready via start_i/done_o.
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`timescale 1ns/1ps
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module tb_mlkem_kg_kat_xsim;
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reg clk=0, rst_n=0, start_i=0;
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reg [255:0] d_i, z_i;
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wire busy_o, done_o;
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reg [3:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
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reg dbg_byte_sel_i=0; reg [9:0] dbg_byte_idx_i=0; wire [7:0] dbg_byte_o;
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reg [11:0] dbg_dk_idx_i=0; wire [7:0] dbg_dk_o;
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wire [255:0] dbg_rho_o, dbg_sigma_o;
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mlkem_top #(.K(2)) dut (
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.clk(clk), .rst_n(rst_n), .d_i(d_i), .z_i(z_i), .start_i(start_i),
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.busy_o(busy_o), .done_o(done_o),
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.dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
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.dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
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.dbg_dk_idx_i(dbg_dk_idx_i), .dbg_dk_o(dbg_dk_o),
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.dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o)
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);
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always #5 clk = ~clk;
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// KAT count=0 (byte0-low literals)
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localparam [255:0] D_LIT = 256'h2426f1941779574d3f1b163bd57f7e173e229e630ec7f7073bdf365137c4bb6d;
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localparam [255:0] Z_LIT = 256'h687acf9406694974d383032f7579378f449c75d0560af56cf921ec48404896f6;
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reg [7:0] ek_gold [0:799];
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reg [7:0] dk_gold [0:1631];
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integer c, i, errors;
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initial begin
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$readmemh("sync_rtl/top/TB/vectors/c000_ek_bytes.hex", ek_gold);
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$readmemh("sync_rtl/top/TB/vectors/c000_dk_full_bytes.hex", dk_gold);
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d_i = D_LIT; z_i = Z_LIT;
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rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
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start_i=1; @(posedge clk); start_i=0;
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c=0; while(!done_o && c<600000) begin @(posedge clk); c=c+1; end
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if(!done_o) begin $display("FAIL: timeout after %0d cyc", c); $finish; end
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$display("=== Stage 4: ML-KEM-512 KeyGen end-to-end vs NIST KAT === done in %0d cyc", c);
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errors = 0;
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// ek == KAT pk (800B)
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dbg_byte_sel_i = 1'b0;
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for (i = 0; i < 800; i = i + 1) begin
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dbg_byte_idx_i = i[9:0]; @(posedge clk); @(posedge clk);
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if (dbg_byte_o !== ek_gold[i]) begin
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if (errors < 8) $display(" EK[%0d] got=%02x exp=%02x", i, dbg_byte_o, ek_gold[i]);
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errors = errors + 1;
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end
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end
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// dk == KAT sk (1632B)
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for (i = 0; i < 1632; i = i + 1) begin
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dbg_dk_idx_i = i[11:0]; @(posedge clk); @(posedge clk);
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if (dbg_dk_o !== dk_gold[i]) begin
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if (errors < 8) $display(" DK[%0d] got=%02x exp=%02x", i, dbg_dk_o, dk_gold[i]);
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errors = errors + 1;
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end
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end
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if (errors == 0) $display("ALL TESTS PASSED: ek==KAT.pk (800B), dk==KAT.sk (1632B)");
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else $display("TESTS FAILED: %0d byte mismatches", errors);
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$finish;
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end
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initial begin #40000000; $display("FAIL: global timeout"); $finish; end
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endmodule
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