FallenSigh
17914911c3
Add ST_E stage: serialize t_hat[0..1] -> ek_mem[0..767], s_hat[0..1] ->
dkp_mem[0..767] via byteEncode12 (2 coeffs -> 3 bytes, LSB-first 12-bit:
b0=c0[7:0], b1={c1[3:0],c0[11:8]}, b2=c1[11:4]), then copy rho into
ek_mem[768..799]. Byte readback tap (dbg_byte_sel/idx -> dbg_byte_o).
Verified vs KAT-derived golden: ek 800B (== KAT pk) + dk_pke 768B
(== KAT sk prefix) byte-exact (20430 cyc). Completes Stage 2 datapath.
67 lines
2.9 KiB
Verilog
67 lines
2.9 KiB
Verilog
// tb_mlkem_kg_2f_xsim.v - Stage 2f: verify byteEncode12 -> ek (800B), dk_pke (768B).
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// ek = byteEncode12(t_hat[0..1]) || rho ; dk_pke = byteEncode12(s_hat[0..1]).
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// Golden: c000_ek.hex (single 1600-hex line), c000_dkpke.hex (1536-hex line).
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`timescale 1ns/1ps
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module tb_mlkem_kg_2f_xsim;
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reg clk=0, rst_n=0, start_i=0;
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reg [255:0] d_i, z_i=0;
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wire busy_o, done_o;
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reg [3:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
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reg dbg_byte_sel_i=0; reg [9:0] dbg_byte_idx_i=0; wire [7:0] dbg_byte_o;
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wire [255:0] dbg_rho_o, dbg_sigma_o;
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mlkem_top #(.K(2)) dut (
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.clk(clk), .rst_n(rst_n), .d_i(d_i), .z_i(z_i), .start_i(start_i),
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.busy_o(busy_o), .done_o(done_o),
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.dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
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.dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
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.dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o)
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);
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always #5 clk = ~clk;
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localparam [255:0] D_LIT = 256'h2426f1941779574d3f1b163bd57f7e173e229e630ec7f7073bdf365137c4bb6d;
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// golden bytes loaded as memories: 1 byte per entry
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reg [7:0] ek_gold [0:799];
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reg [7:0] dkp_gold [0:767];
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integer c, i, errors;
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initial begin
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$readmemh("sync_rtl/top/TB/vectors/c000_ek_bytes.hex", ek_gold);
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$readmemh("sync_rtl/top/TB/vectors/c000_dkpke_bytes.hex", dkp_gold);
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d_i = D_LIT;
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rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
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start_i=1; @(posedge clk); start_i=0;
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c=0; while(!done_o && c<500000) begin @(posedge clk); c=c+1; end
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if(!done_o) begin $display("FAIL: timeout after %0d cyc", c); $finish; end
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$display("=== Stage 2f: byteEncode12 -> ek/dk_pke === done in %0d cyc", c);
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errors = 0;
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// ek: 800 bytes (sel=0)
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dbg_byte_sel_i = 1'b0;
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for (i = 0; i < 800; i = i + 1) begin
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dbg_byte_idx_i = i[9:0];
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@(posedge clk); @(posedge clk);
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if (dbg_byte_o !== ek_gold[i]) begin
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if (errors < 8) $display(" EK MISMATCH[%0d]: got=%02x exp=%02x", i, dbg_byte_o, ek_gold[i]);
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errors = errors + 1;
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end
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end
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// dk_pke: 768 bytes (sel=1)
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dbg_byte_sel_i = 1'b1;
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for (i = 0; i < 768; i = i + 1) begin
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dbg_byte_idx_i = i[9:0];
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@(posedge clk); @(posedge clk);
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if (dbg_byte_o !== dkp_gold[i]) begin
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if (errors < 8) $display(" DKP MISMATCH[%0d]: got=%02x exp=%02x", i, dbg_byte_o, dkp_gold[i]);
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errors = errors + 1;
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end
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end
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if (errors == 0) $display("ALL TESTS PASSED (ek 800B + dk_pke 768B exact)");
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else $display("TESTS FAILED: %0d byte mismatches", errors);
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$finish;
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end
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initial begin #30000000; $display("FAIL: global timeout"); $finish; end
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endmodule
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