FallenSigh
2f206a6bc5
Fresh valid/ready KeyGen FSM for ML-KEM-512 (K=2, eta1=3). Independent keccak per consumer (no arbiter). Verified stage-by-stage vs ml-kem-r golden: - 2a G(d||K): rho/sigma exact (d byte0-low, K at byte32, no reversal). - 2b SampleNTT: A_hat[i][j] from seed rho||j||i, 1024/1024 coeffs exact. - 2c CBD: s[i]=CBD3(PRF(sigma,i)), e[i]=CBD3(PRF(sigma,K+i)); signed->mod-q (+Q when negative); 2048/2048 (A+s+e) coeffs exact. polymem register array (10 slots x 256), debug readback tap (dbg_slot/idx -> coeff, rho/sigma taps) for stage TBs. a_busy/c_busy guards (defensive after sample_ntt fix). FSM: IDLE->G->A->C->DONE (datapath extended in later stages). Plan + progress doc in .claude/plans/keygen_plan.md.
61 lines
2.6 KiB
Verilog
61 lines
2.6 KiB
Verilog
// tb_mlkem_kg_2c_xsim.v - Stage 2c: verify A_hat + s + e stored in mlkem_top.
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// Reads golden kg_c000_AsE.hex (8 polys x 256 = 2048 lines, mod-q) and checks
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// polymem slots A00,A01,A10,A11,S0,S1,E0,E1 via the debug readback tap.
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`timescale 1ns/1ps
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module tb_mlkem_kg_2c_xsim;
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reg clk=0, rst_n=0, start_i=0;
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reg [255:0] d_i, z_i=0;
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wire busy_o, done_o;
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reg [3:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
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wire [255:0] dbg_rho_o, dbg_sigma_o;
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mlkem_top #(.K(2)) dut (
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.clk(clk), .rst_n(rst_n), .d_i(d_i), .z_i(z_i), .start_i(start_i),
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.busy_o(busy_o), .done_o(done_o),
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.dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
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.dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o)
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);
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always #5 clk = ~clk;
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localparam [255:0] D_LIT = 256'h2426f1941779574d3f1b163bd57f7e173e229e630ec7f7073bdf365137c4bb6d;
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reg [11:0] gold [0:2047];
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// slot order matches golden file order
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reg [3:0] slot_of [0:7];
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integer c, p, idx, errors, gi;
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initial begin
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$readmemh("sync_rtl/top/TB/vectors/kg_c000_AsE.hex", gold);
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slot_of[0]=4'd0; slot_of[1]=4'd1; slot_of[2]=4'd2; slot_of[3]=4'd3; // A00..A11
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slot_of[4]=4'd4; slot_of[5]=4'd5; // S0,S1
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slot_of[6]=4'd6; slot_of[7]=4'd7; // E0,E1
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d_i = D_LIT;
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rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
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start_i=1; @(posedge clk); start_i=0;
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c=0; while(!done_o && c<200000) begin @(posedge clk); c=c+1; end
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if(!done_o) begin $display("FAIL: timeout after %0d cyc", c); $finish; end
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$display("=== Stage 2c: A_hat + s + e (8 polys) === done in %0d cyc", c);
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errors = 0;
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for (p = 0; p < 8; p = p + 1) begin
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for (idx = 0; idx < 256; idx = idx + 1) begin
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dbg_slot_i = slot_of[p];
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dbg_idx_i = idx[7:0];
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@(posedge clk); @(posedge clk); // 2 cyc for registered readback
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gi = p*256 + idx;
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if (dbg_coeff_o !== gold[gi]) begin
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if (errors < 8)
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$display(" MISMATCH slot%0d[%0d]: got=%03x exp=%03x",
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slot_of[p], idx, dbg_coeff_o, gold[gi]);
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errors = errors + 1;
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end
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end
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end
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if (errors == 0) $display("ALL TESTS PASSED (2048/2048 coeffs)");
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else $display("TESTS FAILED: %0d mismatches", errors);
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$finish;
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end
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initial begin #5000000; $display("FAIL: global timeout"); $finish; end
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endmodule
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