FallenSigh
2f206a6bc5
Fresh valid/ready KeyGen FSM for ML-KEM-512 (K=2, eta1=3). Independent keccak per consumer (no arbiter). Verified stage-by-stage vs ml-kem-r golden: - 2a G(d||K): rho/sigma exact (d byte0-low, K at byte32, no reversal). - 2b SampleNTT: A_hat[i][j] from seed rho||j||i, 1024/1024 coeffs exact. - 2c CBD: s[i]=CBD3(PRF(sigma,i)), e[i]=CBD3(PRF(sigma,K+i)); signed->mod-q (+Q when negative); 2048/2048 (A+s+e) coeffs exact. polymem register array (10 slots x 256), debug readback tap (dbg_slot/idx -> coeff, rho/sigma taps) for stage TBs. a_busy/c_busy guards (defensive after sample_ntt fix). FSM: IDLE->G->A->C->DONE (datapath extended in later stages). Plan + progress doc in .claude/plans/keygen_plan.md.
46 lines
1.9 KiB
Verilog
46 lines
1.9 KiB
Verilog
// tb_mlkem_kg_2a_xsim.v - Stage 2a: verify G(d||K) -> rho/sigma in mlkem_top.
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`timescale 1ns/1ps
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module tb_mlkem_kg_2a_xsim;
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reg clk=0, rst_n=0, start_i=0;
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reg [255:0] d_i, z_i=0;
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wire busy_o, done_o;
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reg [3:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
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wire [255:0] dbg_rho_o, dbg_sigma_o;
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mlkem_top #(.K(2)) dut (
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.clk(clk), .rst_n(rst_n), .d_i(d_i), .z_i(z_i), .start_i(start_i),
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.busy_o(busy_o), .done_o(done_o),
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.dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
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.dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o)
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);
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always #5 clk = ~clk;
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localparam [255:0] D_LIT = 256'h2426f1941779574d3f1b163bd57f7e173e229e630ec7f7073bdf365137c4bb6d;
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localparam [255:0] RHO_EXP = 256'h15f74355ca862c3cdf3dab780c35cf24b88bf144706090a1c17e41205f9f1379;
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localparam [255:0] SIG_EXP = 256'h69b042001b5630b1a039116cbfd29f62c0bde5a6b571504a9fcce68bed667fd5;
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integer c;
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initial begin
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d_i = D_LIT;
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rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
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start_i=1; @(posedge clk); start_i=0;
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c=0; while(!done_o && c<1000) begin @(posedge clk); c=c+1; end
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if(!done_o) begin $display("FAIL: timeout"); $finish; end
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$display("=== Stage 2a: G(d||K) ===");
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if (dbg_rho_o===RHO_EXP && dbg_sigma_o===SIG_EXP) begin
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$display("PASS: rho = %064x", dbg_rho_o);
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$display("PASS: sigma = %064x", dbg_sigma_o);
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$display("ALL TESTS PASSED");
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end else begin
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$display("FAIL:");
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$display(" rho got=%064x", dbg_rho_o);
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$display(" rho exp=%064x", RHO_EXP);
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$display(" sig got=%064x", dbg_sigma_o);
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$display(" sig exp=%064x", SIG_EXP);
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end
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$finish;
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end
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initial begin #50000; $display("FAIL: global timeout"); $finish; end
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endmodule
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