FallenSigh d8d57db82a optimize

2026-07-11 17:21:21 +08:00

..

vectors

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

2026-06-25 20:48:38 +08:00

gen_vectors.py

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

2026-06-25 20:48:38 +08:00

tb_poly_mul_xsim.v

fix(tb): fix Vivado 2019.2 compilation and TB timing bugs

2026-06-25 21:32:19 +08:00

xsim_run.tcl

optimize

2026-07-11 17:21:21 +08:00