FallenSigh
d4c3fc86fc
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
49 lines
1.5 KiB
Tcl
49 lines
1.5 KiB
Tcl
# xsim_run.tcl - Vivado xsim compilation and simulation script
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#
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# Compiles s_bram, sd_bram, and tb_storage_xsim testbench.
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# Run from the project root: ~/Dev/mlkem/
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#
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# Prerequisites:
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# source /opt/Xilinx/Vivado/2019.2/settings64.sh
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#
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# Usage:
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# xsim -runall xsim_run.tcl
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# vivado -mode batch -source xsim_run.tcl
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# ================================================================
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# Configuration
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# ================================================================
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set SRC_DIR sync_rtl/storage
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set TB_DIR sync_rtl/storage/TB
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# ================================================================
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# Step 1: Compile RTL sources (xvlog)
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# ================================================================
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puts "=== Compiling RTL sources ==="
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xvlog -sv ${SRC_DIR}/s_bram.v
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xvlog -sv ${SRC_DIR}/sd_bram.v
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# ================================================================
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# Step 2: Compile testbench
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# ================================================================
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puts "=== Compiling testbench ==="
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xvlog -sv ${TB_DIR}/tb_storage_xsim.v
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# ================================================================
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# Step 3: Elaborate snapshot (xelab)
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# ================================================================
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puts "=== Elaborating snapshot ==="
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xelab tb_storage_xsim -s tb_storage_xsim
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# ================================================================
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# Step 4: Run simulation
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# ================================================================
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puts "=== Running storage test ==="
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xsim tb_storage_xsim -R
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puts ""
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puts "=== Storage simulation complete ==="
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