FallenSigh 5941fee980 feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs ...

Phase 1 complete — all 4 leaf modules verified:
- rng_sync.v: 256-bit Galois LFSR PRNG (10/10 PASS)
- sample_cbd_sync.v: CBD sampler with keccak_core PRF (2560/2560 PASS)
- sample_ntt_sync.v: SHAKE-128 rejection sampling for A matrix (1536/1536 PASS)
- xsim Verilog TBs for sha3 module (tb_sha3_xsim.v, tb_sha3_xsim_simple.v, tb_keccak_core_xsim.v)

2026-06-24 21:32:53 +08:00

..

tb_keccak_core_xsim.v

feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs

2026-06-24 21:32:53 +08:00

tb_sha3_xsim_simple.v

feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs

2026-06-24 21:32:53 +08:00

tb_sha3_xsim.v

feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs

2026-06-24 21:32:53 +08:00

tb_sha3.cpp

feat(sha3): implement synchronous Keccak-f[1600] core with G/H/J modes

2026-06-24 20:33:44 +08:00

xsim_run.tcl

feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs

2026-06-24 21:32:53 +08:00