FallenSigh d4c3fc86fc feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules ...

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

2026-06-25 20:48:38 +08:00

..

vectors

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

2026-06-25 20:48:38 +08:00

gen_vectors.py

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

2026-06-25 20:48:38 +08:00

tb_sample_ntt_xsim.v

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

2026-06-25 20:48:38 +08:00

tb_sample_ntt.cpp

feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs

2026-06-24 21:32:53 +08:00

xsim_run.tcl

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

2026-06-25 20:48:38 +08:00