FallenSigh
cdc5ce25b1
ST_ENC_C reuses the ST_C CBD datapath with Encaps muxes: seed=r (not sigma),
eta=eta1 for y[0..K-1] then eta2 for e1[0..K-1]/e2, nonce 0..2K. 2K+1 polys
(vs KeyGen 2K). y/e1 -> bank_se rel slots 0..2K-1; e2 -> bank_t rel slot 0
(free during C/N/U since TDEC is deferred to V-prep so the 28-slot banks hold
all of A+y_hat+e1+e2 at K=4 without resizing).
Bring-up golden via ml-kem-r dump_encaps_full (working-tree example):
vectors/encgold/ec_k2_c0_{y,e1,e2}.hex. Verified (K=2 c0) y[0..1],e1[0..1],e2
== ml-kem-r; A_hat (E1) and ss (E0) still pass; K=3/4 no timeout.
168 lines
8.0 KiB
Verilog
168 lines
8.0 KiB
Verilog
// tb_mlkem_enc_katK_xsim.v - ML-KEM Encaps vs NIST KAT, parametric K (KP) + CASE.
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// E0 stage: verify H(ek), G(m||H(ek)) -> (ss=K, r). Preloads ek into ek_bram,
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// pulses start with op=1, waits for done, checks ss == KAT.ss and dumps H(ek)/r.
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//
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// xelab -generic_top KP=2|3|4 ; xsim -testplusarg CASE=n
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// ek/m/ct/ss vectors: sync_rtl/top/TB/vectors/enc_k{K}_c{N}_{ek,m,ct,ss}.hex
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// (per-byte hex, byte 0 first).
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`timescale 1ns/1ps
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module tb_mlkem_enc_katK_xsim;
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parameter KP = 2;
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localparam EKB = 384*KP + 32; // ek (=pk) bytes
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localparam CTB = (KP==4) ? 1568 : (32*(10*KP+4)); // ct bytes: K2 768,K3 1088,K4 1568
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reg clk=0, rst_n=0, start_i=0;
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reg [2:0] k_i;
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reg [255:0] d_i, z_i, m_i;
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wire busy_o, done_o;
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// ek preload port
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reg ek_in_we=0; reg [10:0] ek_in_addr=0; reg [7:0] ek_in_byte=0;
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wire [255:0] ss_o;
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reg [10:0] dbg_ct_idx_i=0; wire [7:0] dbg_ct_o;
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reg [3:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
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reg dbg_byte_sel_i=0; reg [10:0] dbg_byte_idx_i=0; wire [7:0] dbg_byte_o;
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reg [11:0] dbg_dk_idx_i=0; wire [7:0] dbg_dk_o;
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wire [255:0] dbg_rho_o, dbg_sigma_o, dbg_r_o, dbg_hek_o;
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mlkem_top dut (
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.clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(1'b1),
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.d_i(d_i), .z_i(z_i), .msg_i(m_i), .start_i(start_i),
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.busy_o(busy_o), .done_o(done_o),
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.ek_in_we(ek_in_we), .ek_in_addr(ek_in_addr), .ek_in_byte(ek_in_byte),
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.ss_o(ss_o), .dbg_ct_idx_i(dbg_ct_idx_i), .dbg_ct_o(dbg_ct_o),
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.dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
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.dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
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.dbg_dk_idx_i(dbg_dk_idx_i), .dbg_dk_o(dbg_dk_o),
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.dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o),
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.dbg_r_o(dbg_r_o), .dbg_hek_o(dbg_hek_o)
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);
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always #5 clk = ~clk;
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reg [7:0] ek_b [0:EKB-1];
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reg [7:0] m_b [0:31];
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reg [7:0] ss_b [0:31];
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integer c, i, errors, casenum, j;
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reg [8*80-1:0] tag, ekfile, mfile, ssfile;
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initial begin
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if (!$value$plusargs("CASE=%d", casenum)) casenum = 0;
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$sformat(tag, "k%0d", KP);
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$sformat(ekfile, "sync_rtl/top/TB/vectors/enc_%0s_c%0d_ek.hex", tag, casenum);
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$sformat(mfile, "sync_rtl/top/TB/vectors/enc_%0s_c%0d_m.hex", tag, casenum);
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$sformat(ssfile, "sync_rtl/top/TB/vectors/enc_%0s_c%0d_ss.hex", tag, casenum);
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$readmemh(ekfile, ek_b);
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$readmemh(mfile, m_b);
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$readmemh(ssfile, ss_b);
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// build m_i: byte i in m_i[8*i +: 8]
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m_i = 256'd0;
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for (j = 0; j < 32; j = j + 1) m_i[8*j +: 8] = m_b[j];
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k_i = KP[2:0];
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$display("=== ML-KEM K=%0d Encaps KAT case %0d (E0) ===", KP, casenum);
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$write(" m = "); for (j=0;j<32;j=j+1) $write("%02x", m_b[j]); $write("\n");
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rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
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// ---- preload ek into ek_bram (1 byte/cycle) ----
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for (i = 0; i < EKB; i = i + 1) begin
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ek_in_we = 1'b1; ek_in_addr = i[10:0]; ek_in_byte = ek_b[i];
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@(posedge clk);
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end
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ek_in_we = 1'b0; @(posedge clk);
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// ---- run Encaps ----
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start_i=1; @(posedge clk); start_i=0;
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c=0; while(!done_o && c<2000000) begin @(posedge clk); c=c+1; end
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if(!done_o) begin $display("FAIL K=%0d case %0d: timeout", KP, casenum); $finish; end
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$display("=== Encaps E0 done in %0d cyc ===", c);
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$write(" H(ek) = "); for (j=0;j<32;j=j+1) $write("%02x", dbg_hek_o[8*j +: 8]); $write("\n");
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$write(" r = "); for (j=0;j<32;j=j+1) $write("%02x", dbg_r_o[8*j +: 8]); $write("\n");
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$write(" ss = "); for (j=0;j<32;j=j+1) $write("%02x", ss_o[8*j +: 8]); $write("\n");
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// ---- check ss == KAT.ss ----
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errors = 0;
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for (j = 0; j < 32; j = j + 1)
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if (ss_o[8*j +: 8] !== ss_b[j]) begin
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if (errors < 8) $display(" SS[%0d] got=%02x exp=%02x", j, ss_o[8*j +: 8], ss_b[j]);
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errors = errors + 1;
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end
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if (errors == 0) $display("K=%0d CASE %0d PASS (E0): ss == KAT.ss", KP, casenum);
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else $display("K=%0d CASE %0d FAIL (E0): %0d ss mismatches", KP, casenum, errors);
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// ---- E1: verify A_hat (slots 0..K^2-1). t_hat (byteDecode12) is re-
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// verified at E6 (V uses it); TDEC is deferred to V-prep so e2 can use
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// bank_t during C/N/U. A_hat equals KeyGen golden (K=2 c0). ----
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// ---- E2: verify y[i], e1[i] (bank_se), e2 (bank_t slot_t) vs ml-kem-r.
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if (KP == 2 && casenum == 0) begin
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verify_e1;
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verify_e2;
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end
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$finish;
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end
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// E1 golden: A_hat[i][j] (KeyGen golden, K=2 c0)
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reg [11:0] ga [0:4*256-1];
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// E2 golden: y0,y1,e1_0,e1_1 (bank_se rel slots 0..3), e2 (bank_t slot 0)
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reg [11:0] gy [0:4*256-1];
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reg [11:0] ge2 [0:255];
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integer ce, slot, idx;
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task verify_e1;
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begin
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$readmemh("test_framework/modules/mlkem_keygen/golden/c000_Ahat_0_0.hex", ga, 0, 255);
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$readmemh("test_framework/modules/mlkem_keygen/golden/c000_Ahat_0_1.hex", ga, 256, 511);
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$readmemh("test_framework/modules/mlkem_keygen/golden/c000_Ahat_1_0.hex", ga, 512, 767);
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$readmemh("test_framework/modules/mlkem_keygen/golden/c000_Ahat_1_1.hex", ga, 768, 1023);
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ce = 0;
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for (slot = 0; slot < 4; slot = slot + 1)
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for (idx = 0; idx < 256; idx = idx + 1) begin
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dbg_slot_i = slot[3:0]; dbg_idx_i = idx[7:0];
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@(posedge clk); @(posedge clk); @(posedge clk);
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if (dbg_coeff_o !== ga[slot*256+idx]) begin
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if (ce < 8) $display(" A[s%0d,%0d] got=%03x exp=%03x", slot, idx, dbg_coeff_o, ga[slot*256+idx]);
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ce = ce + 1;
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end
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end
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if (ce == 0) $display("K=2 CASE 0 PASS (E1): A_hat (1024) == KeyGen golden");
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else $display("K=2 CASE 0 FAIL (E1): %0d A mismatches", ce);
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end
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endtask
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// y[i],e1[i] live in bank_se at rel slots 0..K-1 (y), K..2K-1 (e1).
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// dbg slot for bank_se = slot_s_rt + rel. K=2: slot_s_rt=4 -> y0=4,y1=5,e1_0=6,e1_1=7.
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// e2 lives in bank_t rel slot 0 -> dbg slot = slot_t_rt = 8.
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task verify_e2;
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begin
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$readmemh("sync_rtl/top/TB/vectors/encgold/ec_k2_c0_y_0.hex", gy, 0, 255);
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$readmemh("sync_rtl/top/TB/vectors/encgold/ec_k2_c0_y_1.hex", gy, 256, 511);
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$readmemh("sync_rtl/top/TB/vectors/encgold/ec_k2_c0_e1_0.hex", gy, 512, 767);
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$readmemh("sync_rtl/top/TB/vectors/encgold/ec_k2_c0_e1_1.hex", gy, 768, 1023);
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$readmemh("sync_rtl/top/TB/vectors/encgold/ec_k2_c0_e2.hex", ge2);
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ce = 0;
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// y0,y1,e1_0,e1_1 at bank_se dbg slots 4..7
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for (slot = 0; slot < 4; slot = slot + 1)
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for (idx = 0; idx < 256; idx = idx + 1) begin
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dbg_slot_i = (4+slot); dbg_idx_i = idx[7:0];
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@(posedge clk); @(posedge clk); @(posedge clk);
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if (dbg_coeff_o !== gy[slot*256+idx]) begin
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if (ce < 8) $display(" Y[s%0d,%0d] got=%03x exp=%03x", slot, idx, dbg_coeff_o, gy[slot*256+idx]);
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ce = ce + 1;
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end
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end
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// e2 at bank_t dbg slot 8
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for (idx = 0; idx < 256; idx = idx + 1) begin
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dbg_slot_i = 8; dbg_idx_i = idx[7:0];
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@(posedge clk); @(posedge clk); @(posedge clk);
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if (dbg_coeff_o !== ge2[idx]) begin
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if (ce < 12) $display(" E2[%0d] got=%03x exp=%03x", idx, dbg_coeff_o, ge2[idx]);
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ce = ce + 1;
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end
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end
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if (ce == 0) $display("K=2 CASE 0 PASS (E2): y[0..1],e1[0..1],e2 == ml-kem-r golden");
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else $display("K=2 CASE 0 FAIL (E2): %0d coeff mismatches", ce);
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end
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endtask
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initial begin #120000000; $display("FAIL: global timeout"); $finish; end
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endmodule
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