FallenSigh
4997657d7e
Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now 120/120 vectors. Also ignore .omo/ session runtime cache and archive the 06-27-sha3-g-test-specific-input trellis task. Verified all 10 modules pass both frameworks: - Verilator: 4334/4334 vectors - XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203 Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).
36 lines
495 B
Plaintext
36 lines
495 B
Plaintext
# Verilator build artifacts
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obj_dir/
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*/obj_dir/
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# Python cache
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__pycache__/
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*.pyc
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# Test framework outputs
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test_framework/reports/report_*.html
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test_framework/modules/*/vectors/*.hex
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# XSIM testbench result dumps (regenerated by simulation)
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sync_rtl/**/TB/vectors/*_result.hex
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# Vivado XSIM simulation artifacts
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xsim.dir/
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*.jou
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*.log
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*.pb
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*.wdb
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*.backup.jou
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*.backup.log
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.Xil/
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webtalk*.jou
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webtalk*.log
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xelab.pb
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xvlog.pb
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# OS
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.DS_Store
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Thumbs.db
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# Session runtime continuation cache
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.omo/
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