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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
121 lines
3.2 KiB
C++
121 lines
3.2 KiB
C++
// tb_mod_add.cpp - Verilator C++ testbench for mod_add_sync
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//
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// Reads test vectors from a hex file specified by +VECTOR_FILE= plusarg.
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// Each line: "AAA BBB" (two 12-bit hex operands).
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// Drives the DUT, waits for valid_o, writes "RESULT: CCC" to stdout.
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//
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// Clock: CLK_PERIOD ns period (from defines.vh).
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// Reset: 2 cycles low, then high.
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// Timeout: 100,000 cycles.
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <sstream>
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#include <cstdlib>
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#include "Vmod_add_sync.h"
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#include "verilated.h"
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#define CLK_PERIOD_NS 10.0
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#define TIMEOUT_CYCLES 100000
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#define Q 3329
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static vluint64_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv);
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// Parse +VECTOR_FILE= plusarg
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const char* vector_file = NULL;
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for (int i = 1; i < argc; i++) {
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std::string arg(argv[i]);
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if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
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vector_file = argv[i] + 13; // skip "+VECTOR_FILE="
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}
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}
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if (!vector_file) {
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std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
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return 1;
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}
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std::ifstream infile(vector_file);
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if (!infile.is_open()) {
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std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
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return 1;
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}
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// Instantiate DUT
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Vmod_add_sync* dut = new Vmod_add_sync;
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// Initialize
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dut->clk = 0;
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dut->rst_n = 0;
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dut->a = 0;
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dut->b = 0;
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dut->valid_i = 0;
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dut->ready_i = 0;
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// Reset: 2 cycles low
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for (int i = 0; i < 4; i++) {
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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}
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dut->rst_n = 1;
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// Always ready to receive results
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dut->ready_i = 1;
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std::string line;
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vluint64_t cycle = 0;
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bool waiting_result = false;
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while (std::getline(infile, line)) {
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// Skip empty lines and comments
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if (line.empty() || line[0] == '#') continue;
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// Parse hex operands
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std::istringstream iss(line);
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unsigned int a_val, b_val;
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if (!(iss >> std::hex >> a_val >> b_val)) continue;
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dut->a = a_val & 0xFFF;
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dut->b = b_val & 0xFFF;
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dut->valid_i = 1;
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// posedge: DUT samples valid_i, pipeline_reg captures data, valid_o→1
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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cycle++;
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dut->valid_i = 0;
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// posedge: pipeline_reg clears valid_o (ready_i=1), but result is
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// available on sum port right now (combinational from data_r)
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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cycle++;
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printf("RESULT: %03X\n", dut->sum & 0xFFF);
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}
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infile.close();
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delete dut;
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return 0;
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}
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