FallenSigh
8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
8 lines
297 B
C++
8 lines
297 B
C++
// DESCRIPTION: Generated by verilator_includer via makefile
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#define VL_INCLUDE_OPT include
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#include "Vmod_add_sync.cpp"
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#include "Vmod_add_sync___024root__0.cpp"
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#include "Vmod_add_sync___024root__Slow.cpp"
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#include "Vmod_add_sync___024root__0__Slow.cpp"
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#include "Vmod_add_sync__Syms__Slow.cpp"
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