FallenSigh
03b4707879
- sha3_chain_top_shared.v: external keccak_core interface (6 ports) - sample_cbd_sync_shared.v: shared keccak variant (6 ports) - sample_ntt_sync_shared.v: shared keccak variant (6 ports) - keccak_arbiter.v: fixed-priority arbiter for 3 keccak consumers - mlkem_top.v: 1403-line monolithic FSM with KeyGen/Encaps/Decaps Architecture: keccak_arbiter → keccak_core → keccak_round (shared) sha3_chain_top_shared (consumer 0) sample_cbd_sync_shared (consumer 1) sample_ntt_sync_shared (consumer 2) sha3_top (separate, own keccak_core) rng_sync, ntt_core, poly_arith, poly_mul, comp_decomp, mod_add sd_bram for polynomial storage All original RTL files preserved unchanged.
116 lines
4.6 KiB
Verilog
116 lines
4.6 KiB
Verilog
// sha3_chain_top_shared.v - SHA3-512 chain: G(d||k=2) → rho, sigma
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//
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// Refactored version that accepts an external keccak_core interface instead
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// of instantiating sha3_top internally. Designed for shared-keccak top-level
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// integration where a single keccak_core is time-multiplexed via an arbiter.
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//
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// The internal logic replicates sha3_top's G-mode absorb-state construction
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// and keccak sequencing, but exposes keccak_core signals through the port
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// list so the arbiter can route them.
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//
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// 3-state FSM: IDLE → BUSY → DONE
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//
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// Interface:
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// clk, rst_n - clock, active-low reset
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// d_in[255:0] - 256-bit d input (external, NOT from RNG)
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// start_i - start computation
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// done_o - computation complete (pulsed for duration of DONE)
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// rho_out[255:0] - G output first 256 bits
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// sigma_out[255:0] - G output next 256 bits
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// kc_state_o[1599:0]- from keccak_core output (post-permutation state)
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// kc_valid_o - from keccak_core (permutation complete)
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// kc_ready_i - to keccak_core (always accept output = 1'b1)
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// kc_state_i[1599:0]- to keccak_core input (pre-permutation state)
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// kc_valid_i - to keccak_core (start permutation pulse)
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// kc_ready_o - from keccak_core (core is idle / can accept)
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module sha3_chain_top_shared (
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input clk,
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input rst_n,
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input [255:0] d_in,
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input start_i,
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output done_o,
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output [255:0] rho_out,
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output [255:0] sigma_out,
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// keccak_core interface (connect to shared arbiter)
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input [1599:0] kc_state_o,
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input kc_valid_o,
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output kc_ready_i,
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output [1599:0] kc_state_i,
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output kc_valid_i,
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input kc_ready_o
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);
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localparam ST_IDLE = 2'd0;
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localparam ST_BUSY = 2'd1;
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localparam ST_DONE = 2'd2;
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reg [1:0] state_r, state_next;
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// ================================================================
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// Absorb state: message || suffix || pad10*1 into rate bits
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//
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// Replicates sha3_top G-mode absorb_state construction:
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// data_i = {248'b0, k=8'd2, d_in}
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// G: padded_block = {1'b1, {308{1'b0}}, 1'b1, 2'b10, data_i[263:0]}
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// absorb_state = {1024'b0, padded_block_576}
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// ================================================================
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wire [511:0] sha3_data_i;
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wire [575:0] g_pad;
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wire [1599:0] absorb_state;
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assign sha3_data_i = {248'b0, 8'd2, d_in};
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assign g_pad = {1'b1, {308{1'b0}}, 1'b1, 2'b10, sha3_data_i[263:0]};
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assign absorb_state = {{(1600-576){1'b0}}, g_pad};
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// ================================================================
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// keccak_core interface connections
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// ================================================================
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assign kc_ready_i = 1'b1; // always accept output
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assign kc_state_i = absorb_state; // feed absorb state combinationally
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assign kc_valid_i = (state_next == ST_BUSY); // start keccak on IDLE → BUSY
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// done_o: asserted for duration of DONE state
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assign done_o = (state_r == ST_DONE);
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// ================================================================
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// Output registers
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// ================================================================
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reg [255:0] rho_out_r, sigma_out_r;
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assign rho_out = rho_out_r;
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assign sigma_out = sigma_out_r;
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// ================================================================
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// FSM combinational next-state
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// ================================================================
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always @(*) begin
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state_next = state_r;
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case (state_r)
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ST_IDLE: if (start_i && kc_ready_o) state_next = ST_BUSY;
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ST_BUSY: if (kc_valid_o) state_next = ST_DONE;
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ST_DONE: if (!start_i) state_next = ST_IDLE;
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default: state_next = ST_IDLE;
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endcase
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end
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// ================================================================
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// Sequential logic
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// ================================================================
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_r <= ST_IDLE;
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rho_out_r <= 256'd0;
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sigma_out_r <= 256'd0;
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end else begin
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state_r <= state_next;
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// Capture squeezed output when BUSY → DONE
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if (state_r == ST_BUSY && kc_valid_o) begin
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rho_out_r <= kc_state_o[255:0];
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sigma_out_r <= kc_state_o[511:256];
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end
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end
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end
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endmodule
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