FallenSigh
453bc899fc
Phase 1.1 of ML-KEM sync rewrite. - keccak_round.v: combinational theta/rho/pi/chi/iota - keccak_core.v: 24-round pipeline, valid/ready - sha3_top.v: sponge FSM, modes G(SHA3-512)/H(SHA3-256)/J(SHAKE-256) - Verilator C++ TB + Python vector gen against reference - Verified: 25/25 vectors bit-exact vs Python G()/H()/J()
100 lines
3.5 KiB
Verilog
100 lines
3.5 KiB
Verilog
// keccak_core.v - Synchronous Keccak-f[1600] core with valid/ready
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//
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// Runs 24 rounds of keccak_round on the input state.
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// valid_i high with ready_o high → load state_i, start 24-round sequence.
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// Each round takes 1 cycle. After round 23, valid_o asserted with state_o.
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//
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// Parameter:
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// ROUNDS = 24 (default)
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//
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// Interface:
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// clk, rst_n - clock, active-low reset
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// state_i - 1600-bit input state
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// valid_i - start permutation
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// ready_o - core can accept new input
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// state_o - 1600-bit output state (after permutation)
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// valid_o - output is valid
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// ready_i - consumer accepts output
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module keccak_core #(parameter ROUNDS = 24) (
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input clk,
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input rst_n,
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input [1599:0] state_i,
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input valid_i,
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output ready_o,
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output [1599:0] state_o,
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output valid_o,
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input ready_i
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);
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// ================================================================
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// Internal registers
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// ================================================================
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reg busy_r; // 1 while running permutation
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reg [4:0] cnt_r; // round counter (0 to ROUNDS-1)
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reg [1599:0] state_r; // current state
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// ================================================================
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// Next-state logic
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// ================================================================
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wire cnt_is_last; // cnt_r == ROUNDS-1 ?
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wire [1599:0] state_next; // combinational round output
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assign cnt_is_last = (cnt_r == (ROUNDS - 1));
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// keccak_round: apply one round to current state
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keccak_round u_round (
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.state_i(state_r),
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.round_i(cnt_r),
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.state_o(state_next)
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);
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// ================================================================
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// Valid/ready handshake
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// ================================================================
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// ready_o: accept new input when not busy (or just finishing)
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assign ready_o = !busy_r;
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// valid_o: output valid when we just finished the last round
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// (the final state is already in state_r at the output cycle)
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assign valid_o = busy_r && cnt_is_last;
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// state_o: output the final state
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assign state_o = state_next; // final state from the last round
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// ================================================================
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// Sequential logic
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// ================================================================
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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busy_r <= 1'b0;
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cnt_r <= 5'd0;
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state_r <= 1600'd0;
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end else begin
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if (!busy_r) begin
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// IDLE: wait for valid_i
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if (valid_i) begin
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state_r <= state_i;
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cnt_r <= 5'd0;
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busy_r <= 1'b1;
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end
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end else begin
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// BUSY: running permutations
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if (cnt_is_last) begin
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// Final round: check if output can be accepted
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if (ready_i) begin
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busy_r <= 1'b0;
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cnt_r <= 5'd0;
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end
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// else: hold until ready_i
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end else begin
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// Intermediate round: advance state
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state_r <= state_next;
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cnt_r <= cnt_r + 5'd1;
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end
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end
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end
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end
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endmodule
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