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8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
48 lines
1.3 KiB
Verilog
48 lines
1.3 KiB
Verilog
// mod_add_sync.v - Synchronous modular adder for ML-KEM
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//
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// Computes (a + b) mod Q where Q = 3329.
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// Uses pipeline_reg internally for the computation stage.
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// Result is valid one cycle after valid_i && ready_o.
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//
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// Interface:
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// clk, rst_n - clock, active-low reset
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// a, b - operands (0 <= a,b < Q)
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// valid_i, ready_o, sum, valid_o, ready_i - valid/ready handshake
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`include "sync_rtl/common/defines.vh"
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module mod_add_sync (
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input clk,
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input rst_n,
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input [11:0] a,
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input [11:0] b,
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input valid_i,
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output ready_o,
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output [11:0] sum,
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output valid_o,
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input ready_i
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);
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// Compute (a + b) mod Q
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wire [12:0] add_raw; // 13 bits to hold potential overflow
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wire [11:0] add_sub_q; // (a + b) - Q
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wire [11:0] mod_result; // final (a + b) mod Q
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assign add_raw = {1'b0, a} + {1'b0, b};
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assign add_sub_q = add_raw[11:0] - `Q;
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assign mod_result = (add_raw < `Q) ? add_raw[11:0] : add_sub_q;
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// Pipeline the result through pipeline_reg
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pipeline_reg #(.DW(12)) u_pipe (
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.clk (clk),
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.rst_n (rst_n),
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.data_i (mod_result),
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.valid_i(valid_i),
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.ready_o(ready_o),
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.data_o (sum),
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.valid_o(valid_o),
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.ready_i(ready_i)
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);
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endmodule
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