FallenSigh
79653ac3a5
- Replace -include_dirs . with -i . (Vivado 2019.2 syntax)
- Add --timescale 1ns/1ps to all xelab commands
- Add LD_PRELOAD comment for ncurses compatibility
- Add run_tb.sh convenience script
Usage: ./run_tb.sh mod_add
./run_tb.sh --list
- Update spec with Vivado 2019.2 compatibility notes
64 lines
2.1 KiB
Tcl
64 lines
2.1 KiB
Tcl
# NOTE: On some systems, you may need:
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# export LD_PRELOAD=/usr/lib64/libtinfo.so.5
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# before running this script.
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# xsim_run.tcl - Vivado xsim compilation and simulation script for mod_add_sync
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#
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# Compiles mod_add_sync RTL plus the file-based vector testbench and runs simulation.
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# Run from the project root: ~/Dev/mlkem/
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#
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# Prerequisites:
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# source /opt/Xilinx/Vivado/2019.2/settings64.sh
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#
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# Usage:
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# vivado -mode batch -source sync_rtl/mod_add/TB/xsim_run.tcl
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#
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# # Or step-by-step:
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# xvlog -sv sync_rtl/common/pipeline_reg.v
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# xvlog -sv sync_rtl/mod_add/mod_add_sync.v
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# xvlog -sv sync_rtl/mod_add/TB/tb_mod_add_xsim.v
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# xelab tb_mod_add_xsim -s tb_mod_add_xsim
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# xsim tb_mod_add_xsim -R
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# ================================================================
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# Configuration
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# ================================================================
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set SRC_DIR sync_rtl/mod_add
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set TB_DIR sync_rtl/mod_add/TB
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set COMMON_DIR sync_rtl/common
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# ================================================================
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# Step 1: Compile all source files (xvlog)
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# ================================================================
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puts "=== Compiling RTL sources ==="
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# Common pipeline register
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xvlog -sv -i . ${COMMON_DIR}/pipeline_reg.v
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# mod_add_sync (includes defines.vh from common/)
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xvlog -sv -i . ${SRC_DIR}/mod_add_sync.v
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# ================================================================
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# Step 2: Compile testbench
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# ================================================================
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puts "=== Compiling testbench ==="
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# File-based vector testbench
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xvlog -sv ${TB_DIR}/tb_mod_add_xsim.v
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# ================================================================
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# Step 3: Elaborate snapshot (xelab)
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# ================================================================
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puts "=== Elaborating snapshot ==="
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xelab tb_mod_add_xsim -s tb_mod_add_xsim --timescale 1ns/1ps
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# ================================================================
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# Step 4: Run simulation
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# ================================================================
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puts "=== Running mod_add_sync file-based vector test ==="
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xsim tb_mod_add_xsim -R
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puts ""
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puts "=== mod_add_sync simulation complete ==="
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