FallenSigh
d4c3fc86fc
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
239 lines
8.1 KiB
Verilog
239 lines
8.1 KiB
Verilog
// tb_mod_add_xsim.v - Standard Verilog testbench for mod_add_sync targeting Vivado xsim
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//
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// Reads test vectors from a hex file using $readmemh.
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// Each line is a single 24-bit hex number encoding:
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// bits [23:12] = a, bits [11:0] = b
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//
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// Drives mod_add_sync, waits for valid_o, and writes
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// "RESULT: IDX A B SUM_HEX" to the output file using $fwrite.
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//
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// Parameters:
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// VECTOR_FILE - path to input hex file (default: "vectors/mod_add_input.hex")
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// RESULT_FILE - path to output file (default: "vectors/mod_add_result.hex")
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//
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// Usage:
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// xvlog -sv sync_rtl/common/pipeline_reg.v
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// xvlog -sv sync_rtl/mod_add/mod_add_sync.v
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// xvlog -sv sync_rtl/mod_add/TB/tb_mod_add_xsim.v
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// xelab tb_mod_add_xsim -s tb_mod_add_xsim
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// xsim tb_mod_add_xsim -R
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`timescale 1ns / 1ps
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module tb_mod_add_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/mod_add/TB/vectors/mod_add_input.hex";
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parameter RESULT_FILE = "sync_rtl/mod_add/TB/vectors/mod_add_result.hex";
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parameter MAX_VECTORS = 256;
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parameter TIMEOUT_CYCLES = 1000;
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [11:0] a;
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reg [11:0] b;
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reg valid_i;
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wire ready_o;
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wire [11:0] sum;
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wire valid_o;
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reg ready_i;
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// ================================================================
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// DUT instantiation
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// ================================================================
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mod_add_sync u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.a (a),
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.b (b),
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.valid_i (valid_i),
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.ready_o (ready_o),
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.sum (sum),
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.valid_o (valid_o),
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.ready_i (ready_i)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// ================================================================
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reg [23:0] vector_mem [0:MAX_VECTORS-1];
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer result_fd;
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// Test result tracking
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integer pass_count;
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integer fail_count;
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// ================================================================
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// Hex-to-ASCII conversion helper
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// ================================================================
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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if (nibble < 4'd10)
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nibble_to_ascii = 8'h30 + {4'd0, nibble}; // '0'-'9'
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else
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nibble_to_ascii = 8'h41 + ({4'd0, nibble} - 4'd10); // 'A'-'F'
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end
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endfunction
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// Helper: write 3-hex-digit (12-bit) value to file
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task write_hex_12bit;
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input integer fd;
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input [11:0] val;
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reg [3:0] nib;
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integer j;
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begin
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for (j = 2; j >= 0; j = j - 1) begin
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nib = val[(j*4)+:4];
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$fwrite(fd, "%c", nibble_to_ascii(nib));
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end
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end
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endtask
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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// Count loaded vectors
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vec_count = 0;
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// Load vectors from hex file
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$readmemh(VECTOR_FILE, vector_mem);
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// Count non-x entries to determine actual vector count
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (vector_mem[idx] === 24'hx || vector_mem[idx] === 24'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists and is in the correct format.");
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$display(" Each line: <6 hex chars> = {a[11:0], b[11:0]}");
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Open result file
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result_fd = $fopen(RESULT_FILE, "w");
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if (result_fd == 0) begin
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$display("ERROR: Cannot open result file: %s", RESULT_FILE);
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$finish;
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end
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// Initialize DUT inputs
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a <= 12'd0;
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b <= 12'd0;
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valid_i <= 1'b0;
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ready_i <= 1'b1; // always ready to accept output
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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begin
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reg [11:0] vec_a;
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reg [11:0] vec_b;
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reg [11:0] captured_sum;
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// Extract a and b from memory word
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vec_a = vector_mem[idx][23:12];
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vec_b = vector_mem[idx][11:0];
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$display("INFO: Vector %0d - a=%0d b=%0d", idx, vec_a, vec_b);
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// Drive DUT
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a <= vec_a;
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b <= vec_b;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for valid_o
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cycle_count = 0;
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while (!valid_o && cycle_count < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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end
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if (cycle_count >= TIMEOUT_CYCLES) begin
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$display("ERROR: Timeout waiting for valid_o on vector %0d", idx);
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fail_count = fail_count + 1;
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end else begin
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// Capture sum output
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captured_sum = sum;
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pass_count = pass_count + 1;
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// Write result to output file
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// Format: "RESULT: IDX A_HEX B_HEX SUM_HEX"
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$fwrite(result_fd, "RESULT: %0d ", idx);
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write_hex_12bit(result_fd, vec_a);
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$fwrite(result_fd, " ");
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write_hex_12bit(result_fd, vec_b);
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$fwrite(result_fd, " ");
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write_hex_12bit(result_fd, captured_sum);
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$fwrite(result_fd, "\n");
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end
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// One extra cycle for valid_o handshake
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@(posedge clk);
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end
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end
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// ============================================================
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// Summary
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// ============================================================
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$fclose(result_fd);
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$display("========================================");
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$display("TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display(" Results written to: %s", RESULT_FILE);
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$display("========================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog
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// ================================================================
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initial begin
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#(TIMEOUT_CYCLES * 10 * 100); // TIMEOUT_CYCLES * 10ns per cycle * extra margin
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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