271 lines
11 KiB
Verilog
271 lines
11 KiB
Verilog
// tb_sample_ntt_xsim.v - Vivado xsim FIPS SampleNTT testbench
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//
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// Drives the DUT with test vectors from a hex file and checks every coefficient
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// against the FIPS 203 reference generated by gen_vectors.py.
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//
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// Vector format (packed hex, 66 chars for $readmemh):
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// {j_idx[1:0], i_idx[1:0], k_i[2:0], rho_i[255:0]} (264 bits → 66 hex chars)
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//
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// Usage:
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// xvlog -sv --relax sample_ntt_sync.v TB/tb_sample_ntt_xsim.v
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// xelab tb_sample_ntt_xsim -s tb_sample_ntt_xsim
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// xsim tb_sample_ntt_xsim -R
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//
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// Prerequisites:
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// - Generate vectors: python3 TB/gen_vectors.py
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// - Or refresh expected vectors: python3 TB/gen_vectors.py --refresh-expected
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// - Output files: vectors/sample_ntt_input.hex, vectors/sample_ntt_expected.hex
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`timescale 1ns / 1ps
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module tb_sample_ntt_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/sample_ntt/TB/vectors/sample_ntt_input.hex";
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parameter EXPECTED_FILE = "sync_rtl/sample_ntt/TB/vectors/sample_ntt_expected.hex";
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parameter MAX_VECTORS = 32; // allocation limit for input vectors
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parameter VECTOR_COUNT = 5; // vectors present in VECTOR_FILE
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parameter Q = 3329; // ML-KEM modulus
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parameter N_COEFFS = 256; // coefficients per polynomial
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parameter TIMEOUT = 500000; // per-vector timeout (cycles)
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [255:0] rho_i;
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reg [2:0] k_i;
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reg [1:0] i_idx;
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reg [1:0] j_idx;
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reg valid_i;
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wire ready_o;
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wire [11:0] coeff_o;
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wire valid_o;
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reg ready_i;
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wire last_o;
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// ================================================================
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// DUT instantiation
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// ================================================================
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sample_ntt_sync u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.rho_i (rho_i),
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.k_i (k_i),
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.i_idx (i_idx),
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.j_idx (j_idx),
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.valid_i (valid_i),
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.ready_o (ready_o),
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.coeff_o (coeff_o),
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.valid_o (valid_o),
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.ready_i (ready_i),
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.last_o (last_o)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// ================================================================
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reg [263:0] vector_mem [0:MAX_VECTORS-1];
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reg [11:0] expected_mem [0:MAX_VECTORS*N_COEFFS-1];
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer coeff_idx;
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// Test result tracking
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integer pass_count;
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integer fail_count;
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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// Load vectors from hex file
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$readmemh(VECTOR_FILE, vector_mem);
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$readmemh(EXPECTED_FILE, expected_mem);
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vec_count = VECTOR_COUNT;
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if (vec_count < 1 || vec_count > MAX_VECTORS) begin
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$display("ERROR: VECTOR_COUNT=%0d must be in [1,%0d]",
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vec_count, MAX_VECTORS);
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Initialize DUT inputs
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rho_i <= 256'd0;
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k_i <= 3'd0;
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i_idx <= 2'd0;
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j_idx <= 2'd0;
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valid_i <= 1'b0;
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ready_i <= 1'b1; // always ready to accept output
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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begin
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reg [255:0] vec_rho;
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reg [2:0] vec_k;
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reg [1:0] vec_i;
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reg [1:0] vec_j;
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reg range_ok;
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reg coeff_ok;
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reg last_ok;
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// Extract fields from packed vector_mem
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// vector_mem[263:0] = {1'b0, j_idx, i_idx, k_i, rho_i}
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vec_rho = vector_mem[idx][255:0];
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vec_k = vector_mem[idx][258:256];
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vec_i = vector_mem[idx][260:259];
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vec_j = vector_mem[idx][262:261];
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$display("INFO: Vector %0d - k=%0d, i=%0d, j=%0d, rho[0:31]=%0h...",
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idx, vec_k, vec_i, vec_j, vec_rho[31:0]);
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// Wait for DUT to be IDLE (ready_o high) before driving
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while (!ready_o) begin
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@(posedge clk);
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end
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// Drive DUT with input (1-cycle pulse on valid_i)
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rho_i <= vec_rho;
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k_i <= vec_k;
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i_idx <= vec_i;
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j_idx <= vec_j;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for valid_o stream, collect all 256 coefficients
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coeff_idx = 0;
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cycle_count = 0;
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range_ok = 1'b1; // assume OK until proven otherwise
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coeff_ok = 1'b1;
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last_ok = 1'b1;
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while (coeff_idx < N_COEFFS && cycle_count < TIMEOUT) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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if (valid_o) begin
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if (coeff_o !== expected_mem[idx*N_COEFFS + coeff_idx]) begin
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$display("ERROR: Vector %0d coeff[%0d] mismatch: got=%03h expected=%03h",
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idx, coeff_idx, coeff_o,
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expected_mem[idx*N_COEFFS + coeff_idx]);
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coeff_ok = 1'b0;
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end
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// Check range: coefficient must be in [0, Q-1]
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if (coeff_o >= Q) begin
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$display("ERROR: Vector %0d coeff[%0d]=%0d out of range [0,%0d]",
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idx, coeff_idx, coeff_o, Q-1);
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range_ok = 1'b0;
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end
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if (last_o !== (coeff_idx == N_COEFFS-1)) begin
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$display("ERROR: Vector %0d coeff[%0d] last_o=%b expected=%b",
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idx, coeff_idx, last_o, coeff_idx == N_COEFFS-1);
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last_ok = 1'b0;
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end
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coeff_idx = coeff_idx + 1;
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end
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end
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// Evaluate result
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if (cycle_count >= TIMEOUT) begin
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$display("ERROR: Timeout on vector %0d (got %0d/%0d coefficients)",
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idx, coeff_idx, N_COEFFS);
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fail_count = fail_count + 1;
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end else if (coeff_idx != N_COEFFS) begin
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$display("ERROR: Vector %0d incomplete (got %0d/%0d coefficients)",
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idx, coeff_idx, N_COEFFS);
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fail_count = fail_count + 1;
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end else if (!range_ok) begin
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$display("ERROR: Vector %0d produced out-of-range coefficients",
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idx);
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fail_count = fail_count + 1;
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end else if (!coeff_ok) begin
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$display("ERROR: Vector %0d did not match FIPS SampleNTT",
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idx);
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fail_count = fail_count + 1;
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end else if (!last_ok) begin
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$display("ERROR: Vector %0d asserted last_o on the wrong coefficient",
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idx);
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fail_count = fail_count + 1;
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end else begin
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$display("INFO: Vector %0d PASSED (%0d FIPS-matching coefficients in %0d cycles)",
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idx, coeff_idx, cycle_count);
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pass_count = pass_count + 1;
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end
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// Wait for DUT to return to IDLE before next vector.
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// The DUT may still be processing its last Keccak permutation
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// (ST_WAIT → ST_DONE → ST_IDLE), which takes ~20+ cycles.
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// ASSERTION: after the 256th coeff (last_o), valid_o must stay
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// low until IDLE — any extra pulse is a spurious 257th output
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// (regression guard for the phase-1 need_more fix).
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begin
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integer extra_pulses;
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extra_pulses = 0;
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while (!ready_o) begin
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@(posedge clk);
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if (valid_o) extra_pulses = extra_pulses + 1;
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end
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if (extra_pulses != 0) begin
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$display("ERROR: Vector %0d emitted %0d spurious valid_o pulse(s) after last_o",
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idx, extra_pulses);
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fail_count = fail_count + 1;
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if (pass_count > 0) pass_count = pass_count - 1; // revoke the earlier PASS
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end
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end
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end // inner begin block
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end
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// ============================================================
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// Summary
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// ============================================================
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$display("========================================");
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$display("TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display("========================================");
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if (fail_count > 0) begin
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$display("ERROR: %0d vector(s) FAILED", fail_count);
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$finish;
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end else begin
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$display("ALL VECTORS PASSED");
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$finish;
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end
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end
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// ================================================================
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// Global simulation watchdog
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// ================================================================
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initial begin
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#(TIMEOUT * 10 * 200); // generous global timeout
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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