106 lines
3.6 KiB
Verilog
106 lines
3.6 KiB
Verilog
// comp_decomp_sync.v - ML-KEM coefficient compression/decompression
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//
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// Streaming valid/ready interface. Compression is intentionally iterative to
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// avoid inferring a long combinational divider for /Q.
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// mode=0: compress — round((2^d * x) / Q) mod 2^d
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// mode=1: decompress — round((Q * x) / 2^d)
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// Uses round-half-up (round(2.5)=3, round(3.5)=4).
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// Integer arithmetic:
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// compress: (x * 2^d + Q/2) / Q, lower d bits as result
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// decompress: (x * Q + 2^(d-1)) / 2^d, result (always < Q)
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`include "sync_rtl/common/defines.vh"
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(* use_dsp = "no" *)
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module comp_decomp_sync (
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input clk,
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input rst_n,
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input [11:0] coeff_in,
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input [4:0] d,
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input mode, // 0=compress, 1=decompress
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input valid_i,
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output ready_o,
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output [11:0] coeff_out,
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output valid_o,
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input ready_i
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);
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localparam [11:0] Q_VAL = 12'(`Q);
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localparam [4:0] COMP_MSB = 5'd22; // max ((Q-1)<<11)+Q/2 is 23 bits
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reg busy_r;
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reg [4:0] bit_idx_r;
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reg [4:0] d_r;
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reg [23:0] dividend_r;
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reg [23:0] quotient_r;
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reg [12:0] rem_r;
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reg [11:0] data_r;
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reg valid_r;
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wire fire_i = valid_i && ready_o;
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// Accept a new command only when the iterative divider and output slot are
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// both free. Current users tie ready_i high and issue one coefficient at a
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// time, but this keeps the module from accepting work it cannot retain.
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assign ready_o = !busy_r && (!valid_r || ready_i);
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assign coeff_out = data_r;
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assign valid_o = valid_r;
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wire [23:0] comp_dividend = ({12'd0, coeff_in} << d) + 24'd1664;
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wire [23:0] decomp_product =
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{12'd0, coeff_in} +
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({12'd0, coeff_in} << 8) +
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({12'd0, coeff_in} << 10) +
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({12'd0, coeff_in} << 11);
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wire [23:0] decomp_rounded = decomp_product + (24'd1 << (d - 1'b1));
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wire [11:0] decomp_result = decomp_rounded >> d;
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wire [12:0] rem_shift = {rem_r[11:0], dividend_r[bit_idx_r]};
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wire rem_ge_q = rem_shift >= {1'b0, Q_VAL};
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wire [12:0] rem_sub_q = rem_shift - {1'b0, Q_VAL};
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wire [12:0] rem_next = rem_ge_q ? rem_sub_q : rem_shift;
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wire [23:0] quot_next = quotient_r | (rem_ge_q ? (24'd1 << bit_idx_r) : 24'd0);
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wire [11:0] comp_mask = (12'd1 << d_r) - 12'd1;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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busy_r <= 1'b0;
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bit_idx_r <= 5'd0;
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d_r <= 5'd0;
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dividend_r <= 24'd0;
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quotient_r <= 24'd0;
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rem_r <= 13'd0;
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data_r <= 12'd0;
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valid_r <= 1'b0;
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end else begin
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if (valid_r && ready_i)
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valid_r <= 1'b0;
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if (busy_r) begin
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rem_r <= rem_next;
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quotient_r <= quot_next;
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if (bit_idx_r == 5'd0) begin
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busy_r <= 1'b0;
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data_r <= quot_next[11:0] & comp_mask;
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valid_r <= 1'b1;
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end else begin
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bit_idx_r <= bit_idx_r - 5'd1;
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end
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end else if (fire_i) begin
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if (mode) begin
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data_r <= decomp_result;
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valid_r <= 1'b1;
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end else begin
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busy_r <= 1'b1;
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bit_idx_r <= COMP_MSB;
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d_r <= d;
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dividend_r <= comp_dividend;
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quotient_r <= 24'd0;
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rem_r <= 13'd0;
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end
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end
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end
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end
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endmodule
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