Scaffolding for ML-KEM Decaps (FIPS 203 Alg 18):
- op_i widened to 2-bit: 00=KeyGen, 01=Encaps, 10=Decaps (op_r too).
- New ST_DEC_LOAD state (D0: settles to DONE so load/parse is dbg-checkable).
- dk (=sk) streamed via dk_in_*; load logic routes each byte by region:
[0,384K)->dk_pke (dkp_bram), [384K,768K+32)->ek_pke (ek_bram),
[768K+32,+32)->H(ek) (hek_r), [768K+64,+32)->z (z_r). Routing uses the
LIVE k_i input, not start-captured k_r (dk is streamed before start_i).
- c (=ct) streamed via c_in_* into a SEPARATE c_in_bram, so the computed c'
(ct_bram) can later be compared against original c and J(z||c) can read c.
- New dbg taps: dbg_mprime_o/dbg_kbar_o/dbg_decz_o/dbg_dech_o.
TB: tb_mlkem_dec_katK_xsim verifies dk parse (H(ek), z, ek_pke/dk_pke BRAM
round-trip). gen_decaps_vectors.py emits dec_k{K}_c{N}_{dk,ct,ss,ctn,ssn}.hex
from the NIST KAT. run_tb.sh gains a 'dec' module (mirrors 'enc').
Regression fix: old KeyGen/Encaps TBs didn't connect the new input ports,
floating them to X and corrupting the ek/dkp write muxes -> tied off
dk_in_*/c_in_*/new dbg taps in both.
Verified: dec D0 K=2/3/4 PASS; KeyGen K=2 + Encaps K=2 unregressed.
117 lines
5.3 KiB
Verilog
117 lines
5.3 KiB
Verilog
// tb_mlkem_kg_katK_xsim.v - ML-KEM KeyGen vs NIST KAT, parametric K (KP) + CASE.
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// xelab -generic_top KP=2|3|4 ; xsim -testplusarg CASE=n
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// KP=2 -> k2 vectors (ML-KEM-512), KP=3 -> k3 (768), KP=4 -> k4 (1024).
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// ek = 384*KP+32 bytes (==KAT pk), dk = 768*KP+96 bytes (==KAT sk).
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`timescale 1ns/1ps
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module tb_mlkem_kg_katK_xsim;
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parameter KP = 2;
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localparam EKB = 384*KP + 32;
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localparam DKB = 768*KP + 96;
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reg clk=0, rst_n=0, start_i=0;
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reg [2:0] k_i;
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reg [255:0] d_i, z_i;
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wire busy_o, done_o;
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reg [3:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
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reg dbg_byte_sel_i=0; reg [10:0] dbg_byte_idx_i=0; wire [7:0] dbg_byte_o;
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reg [11:0] dbg_dk_idx_i=0; wire [7:0] dbg_dk_o;
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wire [255:0] dbg_rho_o, dbg_sigma_o;
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// KMAX defaults to 4 (worst-case sizing); KP selects the runtime k value.
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mlkem_top dut (
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.clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(2'd0),
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.d_i(d_i), .z_i(z_i), .msg_i(256'd0), .start_i(start_i),
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.busy_o(busy_o), .done_o(done_o),
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.ek_in_we(1'b0), .ek_in_addr(11'd0), .ek_in_byte(8'd0),
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.dk_in_we(1'b0), .dk_in_addr(12'd0), .dk_in_byte(8'd0),
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.c_in_we(1'b0), .c_in_addr(11'd0), .c_in_byte(8'd0),
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.ss_o(), .dbg_ct_idx_i(11'd0), .dbg_ct_o(),
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.dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
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.dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
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.dbg_dk_idx_i(dbg_dk_idx_i), .dbg_dk_o(dbg_dk_o),
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.dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o),
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.dbg_r_o(), .dbg_hek_o(),
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.dbg_mprime_o(), .dbg_kbar_o(), .dbg_decz_o(), .dbg_dech_o()
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);
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always #5 clk = ~clk;
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reg [255:0] dmem [0:0];
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reg [255:0] zmem [0:0];
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reg [7:0] ek_gold [0:EKB-1];
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reg [7:0] dk_gold [0:DKB-1];
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reg [7:0] ek_got [0:EKB-1]; // ek bytes read back from DUT
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reg [7:0] dk_got [0:DKB-1]; // dk bytes read back from DUT
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integer c, i, errors, casenum, j;
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reg [8*80-1:0] tag, dfile, zfile, ekfile, dkfile;
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// Dump a byte array as offset-prefixed hex, 32 bytes/line.
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task dump_bytes(input [8*16-1:0] name, input integer n);
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integer a, b;
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begin
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for (a = 0; a < n; a = a + 32) begin
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$write(" %0s[%4d] ", name, a);
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for (b = a; b < a+32 && b < n; b = b + 1) begin
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if (name == "ek") $write("%02x", ek_got[b]);
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else $write("%02x", dk_got[b]);
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end
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$write("\n");
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end
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end
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endtask
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initial begin
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if (!$value$plusargs("CASE=%d", casenum)) casenum = 0;
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$sformat(tag, "k%0d", KP);
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$sformat(dfile, "sync_rtl/top/TB/vectors/kat_%0s_c%0d_d.hex", tag, casenum);
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$sformat(zfile, "sync_rtl/top/TB/vectors/kat_%0s_c%0d_z.hex", tag, casenum);
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$sformat(ekfile, "sync_rtl/top/TB/vectors/kat_%0s_c%0d_ek.hex", tag, casenum);
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$sformat(dkfile, "sync_rtl/top/TB/vectors/kat_%0s_c%0d_dk.hex", tag, casenum);
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$readmemh(dfile, dmem);
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$readmemh(zfile, zmem);
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$readmemh(ekfile, ek_gold);
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$readmemh(dkfile, dk_gold);
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d_i = dmem[0]; z_i = zmem[0];
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k_i = KP[2:0];
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// ---- show the KeyGen inputs (d, z seeds: 32 bytes each, MSB-first) ----
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$display("=== ML-KEM K=%0d KAT case %0d INPUTS ===", KP, casenum);
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$write(" d = "); for (j = 0; j < 32; j = j + 1) $write("%02x", d_i[8*(31-j) +: 8]); $write("\n");
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$write(" z = "); for (j = 0; j < 32; j = j + 1) $write("%02x", z_i[8*(31-j) +: 8]); $write("\n");
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rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
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start_i=1; @(posedge clk); start_i=0;
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c=0; while(!done_o && c<2000000) begin @(posedge clk); c=c+1; end
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if(!done_o) begin $display("FAIL K=%0d case %0d: timeout", KP, casenum); $finish; end
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$display("=== ML-KEM K=%0d KAT case %0d: KeyGen done in %0d cyc ===", KP, casenum, c);
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errors = 0;
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dbg_byte_sel_i = 1'b0;
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for (i = 0; i < EKB; i = i + 1) begin
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dbg_byte_idx_i = i[10:0]; @(posedge clk); @(posedge clk);
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ek_got[i] = dbg_byte_o;
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if (dbg_byte_o !== ek_gold[i]) begin
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if (errors < 8) $display(" EK[%0d] got=%02x exp=%02x", i, dbg_byte_o, ek_gold[i]);
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errors = errors + 1;
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end
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end
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for (i = 0; i < DKB; i = i + 1) begin
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dbg_dk_idx_i = i[11:0]; @(posedge clk); @(posedge clk);
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dk_got[i] = dbg_dk_o;
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if (dbg_dk_o !== dk_gold[i]) begin
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if (errors < 8) $display(" DK[%0d] got=%02x exp=%02x", i, dbg_dk_o, dk_gold[i]);
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errors = errors + 1;
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end
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end
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// ---- show the KeyGen outputs (ek, dk byte strings read from DUT) ----
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$display("=== ML-KEM K=%0d KAT case %0d OUTPUTS ===", KP, casenum);
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$display(" ek (%0d bytes):", EKB); dump_bytes("ek", EKB);
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$display(" dk (%0d bytes):", DKB); dump_bytes("dk", DKB);
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if (errors == 0) $display("K=%0d CASE %0d PASS: ek (%0dB)==pk, dk (%0dB)==sk", KP, casenum, EKB, DKB);
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else $display("K=%0d CASE %0d FAIL: %0d mismatches", KP, casenum, errors);
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$finish;
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end
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initial begin #120000000; $display("FAIL: global timeout"); $finish; end
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endmodule
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