FallenSigh
8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
796 B
796 B
State Management
How state is managed in this project.
Overview
(To be filled by the team)
State Categories
(To be filled by the team)
When to Use Global State
(To be filled by the team)
Server State
(To be filled by the team)
Common Mistakes
(To be filled by the team)