492 lines
19 KiB
Verilog
492 lines
19 KiB
Verilog
// tb_mlkem_top_xsim.v - KAT (Known Answer Test) testbench for mlkem_top
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//
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// Reads FIPS 203 test vectors from hex files using $readmemh.
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// Uses Verilog `force` to inject known d/z/m values into the DUT's
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// internal registers, overriding the internal RNG output for deterministic
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// KAT verification.
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//
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// IMPORTANT: The mlkem_top module has a known design deadlock:
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// sha3_chain_top_shared requires kc_ready_o to transition IDLE→BUSY,
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// but keccak_arbiter requires cons_valid_i[0]=1 before granting it.
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// Workaround: force chain_kc_ready_o wire to 1 during all tests.
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//
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// Input vector format (192 hex chars = 768 bits per line):
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// bits [767:512] = d (256 bits)
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// bits [511:256] = msg (256 bits)
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// bits [255:0] = z (256 bits)
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//
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// Expected output format (6464 hex chars = 25856 bits per line):
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// bits [25855:19456] = pk (800 bytes = 6400 bits)
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// bits [19455:6400] = sk (1632 bytes = 13056 bits)
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// bits [6399:256] = ct (768 bytes = 6144 bits)
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// bits [255:0] = ss (32 bytes = 256 bits)
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//
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// Test flow per vector:
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// 1. Force d_reg and run KeyGen → verify done_o, capture pk/sk
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// 2. Force m_reg and run Encaps → verify done_o, capture ct/K
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// 3. Force z_reg and run Decaps → verify done_o, capture K_dec
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//
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// Usage:
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// xvlog -sv -i . <all_deps>.v tb_mlkem_top_xsim.v
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// xelab tb_mlkem_top_xsim -s tb_mlkem_top_xsim --timescale 1ns/1ps
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// xsim tb_mlkem_top_xsim -R
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`timescale 1ns / 1ps
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module tb_mlkem_top_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/top/TB/vectors/mlkem_top_input.hex";
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parameter EXPECTED_FILE = "sync_rtl/top/TB/vectors/mlkem_top_expected.hex";
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parameter MAX_VECTORS = 16;
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parameter TIMEOUT_CYCLES = 10000000; // mlkem_top is SLOW (millions of cycles)
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parameter K_PARAM = 4; // matches DUT K=4
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localparam PK_WIDTH = 12 * K_PARAM * 256; // 12288
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localparam SK_WIDTH = 12 * K_PARAM * 256; // 12288
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localparam CT_WIDTH = 12 * K_PARAM * 256; // 12288
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// Expected widths for ML-KEM-512 (k=2):
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localparam EXP_PK_WIDTH = 6400; // 800 bytes
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localparam EXP_SK_WIDTH = 13056; // 1632 bytes
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localparam EXP_CT_WIDTH = 6144; // 768 bytes
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localparam EXP_SS_WIDTH = 256; // 32 bytes
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [1:0] mode;
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reg [2:0] i_k;
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reg valid_i;
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wire ready_o;
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wire [PK_WIDTH-1:0] pk_o;
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wire [SK_WIDTH-1:0] sk_o;
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wire pk_valid;
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wire sk_valid;
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wire [CT_WIDTH-1:0] ct_o;
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wire [255:0] K_o;
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wire ct_valid;
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wire K_valid;
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wire [255:0] K_o_dec;
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wire K_valid_dec;
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wire done_o;
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// ================================================================
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// DUT instantiation
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// ================================================================
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mlkem_top #(.K(K_PARAM)) u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.mode (mode),
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.i_k (i_k),
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.valid_i (valid_i),
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.ready_o (ready_o),
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.pk_o (pk_o),
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.sk_o (sk_o),
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.pk_valid (pk_valid),
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.sk_valid (sk_valid),
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.ct_o (ct_o),
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.K_o (K_o),
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.ct_valid (ct_valid),
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.K_valid (K_valid),
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.K_o_dec (K_o_dec),
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.K_valid_dec (K_valid_dec),
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.done_o (done_o)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memories (loaded by $readmemh)
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// ================================================================
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reg [767:0] input_mem [0:MAX_VECTORS-1];
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reg [25855:0] expected_mem [0:MAX_VECTORS-1];
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// ================================================================
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// Test variables
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// ================================================================
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer pass_count;
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integer fail_count;
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integer kg_pass, kg_fail;
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integer en_pass, en_fail;
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integer dc_pass, dc_fail;
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// ================================================================
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// Hex-to-ASCII conversion helper
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// ================================================================
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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if (nibble < 4'd10)
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nibble_to_ascii = 8'h30 + {4'd0, nibble};
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else
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nibble_to_ascii = 8'h41 + ({4'd0, nibble} - 4'd10);
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end
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endfunction
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// ================================================================
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// Print 256-bit value as hex
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// ================================================================
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task print_hex256;
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input [255:0] val;
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input [256*8:1] label;
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integer bit_idx;
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reg [3:0] nib;
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begin
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$write("%s: ", label);
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for (bit_idx = 63; bit_idx >= 0; bit_idx = bit_idx - 1) begin
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nib = val[(bit_idx*4)+:4];
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$write("%c", nibble_to_ascii(nib));
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end
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$write("\n");
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end
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endtask
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// ================================================================
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// Wait for done_o with timeout
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// Sets result_var: 0 = timeout, 1 = got done
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// ================================================================
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integer wfd_result;
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task wait_for_done;
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input [256*8:1] op_name;
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integer cyc;
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begin
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cyc = 0;
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while (!done_o && cyc < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cyc = cyc + 1;
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end
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if (cyc >= TIMEOUT_CYCLES) begin
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$display("ERROR: %s timeout after %0d cycles", op_name, TIMEOUT_CYCLES);
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wfd_result = 0;
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end else begin
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$display("INFO: %s done after %0d cycles", op_name, cyc);
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wfd_result = 1;
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end
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end
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endtask
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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// ------------------------------------------------------------
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// Count loaded vectors
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// ------------------------------------------------------------
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vec_count = 0;
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// Load vectors from hex files
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$readmemh(VECTOR_FILE, input_mem);
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$readmemh(EXPECTED_FILE, expected_mem);
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// Count non-X entries to determine actual vector count
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (input_mem[idx] === 768'hx || input_mem[idx] === 768'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists and is in the correct format.");
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$display(" Each line: <192 hex chars> = d(64) + msg(64) + z(64)");
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$finish;
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end
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$display("====================================================");
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$display("MLKEM_TOP KAT TESTBENCH");
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$display(" Vectors loaded: %0d", vec_count);
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$display(" Input file: %s", VECTOR_FILE);
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$display(" Expected file: %s", EXPECTED_FILE);
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$display(" Timeout: %0d cycles (~%0d ms)",
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TIMEOUT_CYCLES, TIMEOUT_CYCLES * 10 / 1000);
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$display("====================================================");
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// ------------------------------------------------------------
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// Initialize signals
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// ------------------------------------------------------------
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mode <= 2'd0;
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i_k <= 3'd2; // ML-KEM-512
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valid_i <= 1'b0;
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (5) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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// ------------------------------------------------------------
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// WORKAROUND: Force chain_kc_ready_o to break arbiter deadlock
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// The sha3_chain_top_shared module requires kc_ready_o=1 in its
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// ST_IDLE→ST_BUSY transition, but the keccak_arbiter won't
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// assert cons_ready_o[0] until cons_valid_i[0]=1 (which the
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// chain doesn't assert until it reaches ST_BUSY). Deadlock.
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// Forcing chain_kc_ready_o=1 breaks this cycle.
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//
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// WORKAROUND: Force ntt_valid_o to 1 to fix done_o timing issue
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// The mlkem_top FSM uses ntt_done_o to enter the output-read
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// state, but ntt_core asserts done_o AFTER S_OUTPUT completes.
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// Forcing ntt_valid_o=1 lets the FSM complete its output phase.
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// ------------------------------------------------------------
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force u_dut.chain_kc_ready_o = 1'b1;
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force u_dut.ntt_valid_o = 1'b1;
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$display("INFO: Forced chain_kc_ready_o=1 (arbiter deadlock workaround)");
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$display("INFO: Forced ntt_valid_o=1 (ntt done_o timing workaround)");
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// Reset counters
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pass_count = 0;
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fail_count = 0;
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kg_pass = 0; kg_fail = 0;
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en_pass = 0; en_fail = 0;
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dc_pass = 0; dc_fail = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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reg [255:0] d_val, msg_val, z_val;
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reg [EXP_PK_WIDTH-1:0] exp_pk;
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reg [EXP_SK_WIDTH-1:0] exp_sk;
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reg [EXP_CT_WIDTH-1:0] exp_ct;
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reg [EXP_SS_WIDTH-1:0] exp_ss;
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// Extract test vector fields
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d_val = input_mem[idx][767:512];
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msg_val = input_mem[idx][511:256];
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z_val = input_mem[idx][255:0];
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// Extract expected outputs
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exp_ss = expected_mem[idx][0 +: EXP_SS_WIDTH];
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exp_ct = expected_mem[idx][EXP_SS_WIDTH +: EXP_CT_WIDTH];
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exp_sk = expected_mem[idx][EXP_SS_WIDTH + EXP_CT_WIDTH +: EXP_SK_WIDTH];
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exp_pk = expected_mem[idx][EXP_SS_WIDTH + EXP_CT_WIDTH + EXP_SK_WIDTH +: EXP_PK_WIDTH];
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$display("----------------------------------------------------");
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$display("VECTOR %0d (count=%0d)", idx, idx);
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print_hex256(d_val, " d ");
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print_hex256(msg_val, " msg");
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print_hex256(z_val, " z ");
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print_hex256(exp_ss, " expected ss");
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// ========================================================
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// STEP 1: KeyGen (mode=00)
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// ========================================================
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$display("--- KeyGen ---");
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// Force d_reg to KAT value RIGHT NOW (before starting KeyGen)
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// The force persists until we release it
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force u_dut.d_reg = d_val;
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// Start KeyGen
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mode <= 2'b00;
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i_k <= 3'd2;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for done_o
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wait_for_done("KeyGen");
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if (wfd_result) begin
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// Release force now that KeyGen is done
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release u_dut.d_reg;
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// Check pk_valid and sk_valid
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if (pk_valid && sk_valid) begin
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// Check pk output
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if (pk_o[EXP_PK_WIDTH-1:0] == exp_pk) begin
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$display(" PASS: pk matches expected");
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kg_pass = kg_pass + 1;
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end else begin
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$display(" FAIL: pk mismatch");
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print_hex256(pk_o[255:0], " pk[low] ");
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print_hex256(exp_pk[255:0], " exp[low] ");
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kg_fail = kg_fail + 1;
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end
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// Check sk output
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if (sk_o[SK_WIDTH-1:0] == exp_sk[SK_WIDTH-1:0]) begin
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$display(" PASS: sk matches expected");
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end else begin
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$display(" FAIL: sk mismatch");
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kg_fail = kg_fail + 1;
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end
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end else begin
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$display(" FAIL: pk_valid=%b sk_valid=%b", pk_valid, sk_valid);
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kg_fail = kg_fail + 1;
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end
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end else begin
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release u_dut.d_reg;
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$display(" FAIL: KeyGen timeout");
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kg_fail = kg_fail + 1;
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// DUT is stuck. Reset for next operation.
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rst_n <= 1'b0;
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repeat (5) @(posedge clk);
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rst_n <= 1'b1;
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force u_dut.chain_kc_ready_o = 1'b1;
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force u_dut.ntt_valid_o = 1'b1;
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@(posedge clk);
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end
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// Wait for DUT to return to IDLE
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repeat (2) @(posedge clk);
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// ========================================================
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// STEP 2: Encaps (mode=01)
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// ========================================================
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$display("--- Encaps ---");
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// Force m_reg to KAT value
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force u_dut.m_reg = msg_val;
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// Start Encaps
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mode <= 2'b01;
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i_k <= 3'd2;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for done_o
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wait_for_done("Encaps");
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if (wfd_result) begin
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release u_dut.m_reg;
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if (ct_valid && K_valid) begin
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// Check ct output
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if (ct_o[EXP_CT_WIDTH-1:0] == exp_ct) begin
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$display(" PASS: ct matches expected");
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en_pass = en_pass + 1;
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end else begin
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$display(" FAIL: ct mismatch");
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print_hex256(ct_o[255:0], " ct[low] ");
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print_hex256(exp_ct[255:0], " exp[low] ");
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en_fail = en_fail + 1;
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end
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// Check K (shared secret)
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if (K_o == exp_ss) begin
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$display(" PASS: K matches expected ss");
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end else begin
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$display(" FAIL: K mismatch");
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print_hex256(K_o, " K ");
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print_hex256(exp_ss, " exp_ss");
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en_fail = en_fail + 1;
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end
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end else begin
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$display(" FAIL: ct_valid=%b K_valid=%b", ct_valid, K_valid);
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en_fail = en_fail + 1;
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end
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end else begin
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release u_dut.m_reg;
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$display(" FAIL: Encaps timeout");
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en_fail = en_fail + 1;
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// DUT is stuck. Reset for next operation.
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rst_n <= 1'b0;
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repeat (5) @(posedge clk);
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rst_n <= 1'b1;
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force u_dut.chain_kc_ready_o = 1'b1;
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force u_dut.ntt_valid_o = 1'b1;
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@(posedge clk);
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end
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// Wait for DUT to return to IDLE
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repeat (2) @(posedge clk);
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// ========================================================
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// STEP 3: Decaps (mode=10)
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// ========================================================
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$display("--- Decaps ---");
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// Force z_reg to KAT value
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force u_dut.z_reg = z_val;
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// Start Decaps
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mode <= 2'b10;
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i_k <= 3'd2;
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valid_i <= 1'b1;
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@(posedge clk);
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valid_i <= 1'b0;
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// Wait for done_o
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wait_for_done("Decaps");
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if (wfd_result) begin
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release u_dut.z_reg;
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if (K_valid_dec) begin
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$display(" PASS: Decaps completed (K_valid_dec asserted)");
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dc_pass = dc_pass + 1;
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end else begin
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$display(" FAIL: Decaps K_valid_dec not asserted");
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dc_fail = dc_fail + 1;
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end
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end else begin
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release u_dut.z_reg;
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$display(" FAIL: Decaps timeout (placeholder states — expected)");
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dc_fail = dc_fail + 1;
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// Decaps FSM is now stuck. Reset DUT so next vector
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// can start with a clean state.
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rst_n <= 1'b0;
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repeat (5) @(posedge clk);
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rst_n <= 1'b1;
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// Re-apply workaround forces (reset may have cleared them)
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force u_dut.chain_kc_ready_o = 1'b1;
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force u_dut.ntt_valid_o = 1'b1;
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@(posedge clk);
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end
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// Wait for DUT to return to IDLE
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repeat (2) @(posedge clk);
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end
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// ------------------------------------------------------------
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// Release deadlock workarounds
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// ------------------------------------------------------------
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release u_dut.chain_kc_ready_o;
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release u_dut.ntt_valid_o;
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// ============================================================
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// Summary
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// ============================================================
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$display("====================================================");
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$display("TEST COMPLETE");
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$display(" KeyGen: PASS=%0d FAIL=%0d", kg_pass, kg_fail);
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$display(" Encaps: PASS=%0d FAIL=%0d", en_pass, en_fail);
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$display(" Decaps: PASS=%0d FAIL=%0d", dc_pass, dc_fail);
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$display(" Total: PASS=%0d FAIL=%0d",
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kg_pass + en_pass + dc_pass,
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kg_fail + en_fail + dc_fail);
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$display("====================================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog
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// ================================================================
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initial begin
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#(TIMEOUT_CYCLES * 10 * 100); // TIMEOUT_CYCLES * 10ns * extra margin
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$display("FATAL: Global simulation timeout reached (%0d ns)",
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TIMEOUT_CYCLES * 10 * 100);
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$finish;
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end
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endmodule
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