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Phase 1 complete — all 4 leaf modules verified: - rng_sync.v: 256-bit Galois LFSR PRNG (10/10 PASS) - sample_cbd_sync.v: CBD sampler with keccak_core PRF (2560/2560 PASS) - sample_ntt_sync.v: SHAKE-128 rejection sampling for A matrix (1536/1536 PASS) - xsim Verilog TBs for sha3 module (tb_sha3_xsim.v, tb_sha3_xsim_simple.v, tb_keccak_core_xsim.v)
95 lines
2.6 KiB
C++
95 lines
2.6 KiB
C++
// tb_rng.cpp - Verilator C++ testbench for rng_sync
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//
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// Drives valid_i pulses and prints 256-bit LFSR output values.
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// Reads a hex input file to determine how many vectors to generate
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// (one line per vector, content ignored).
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// Prints "RESULT: <64-char hex>" for each output.
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//
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// Clock: 10ns period. Reset: 2 cycles low.
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// Timeout: 100,000 cycles.
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <cstdio>
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#include "Vrng_sync.h"
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#include "verilated.h"
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#define CLK_PERIOD_NS 10.0
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static vluint64_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv);
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// Parse +VECTOR_FILE= plusarg
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const char* vector_file = NULL;
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for (int i = 1; i < argc; i++) {
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std::string arg(argv[i]);
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if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
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vector_file = argv[i] + 13;
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}
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}
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if (!vector_file) {
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std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
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return 1;
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}
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std::ifstream infile(vector_file);
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if (!infile.is_open()) {
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std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
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return 1;
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}
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// Count non-empty, non-comment lines to determine vector count
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int num_vectors = 0;
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std::string line;
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while (std::getline(infile, line)) {
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if (!line.empty() && line[0] != '#')
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num_vectors++;
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}
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infile.close();
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// Instantiate DUT
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Vrng_sync* dut = new Vrng_sync;
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// Initialize
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dut->clk = 0;
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dut->rst_n = 0;
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dut->valid_i = 0;
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dut->ready_i = 0;
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// Reset: 2 cycles low
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for (int i = 0; i < 4; i++) {
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dut->clk = 1; main_time += 5; dut->eval();
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dut->clk = 0; main_time += 5; dut->eval();
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}
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dut->rst_n = 1;
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dut->ready_i = 1;
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// Generate vectors
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for (int n = 0; n < num_vectors; n++) {
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// Drive valid_i and posedge → LFSR advances, valid_o→1
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dut->valid_i = 1;
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dut->clk = 1; main_time += 5; dut->eval();
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dut->clk = 0; main_time += 5; dut->eval();
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dut->valid_i = 0;
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// Posedge to consume → valid_o→0
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dut->clk = 1; main_time += 5; dut->eval();
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// Print 256-bit result (8 × 32-bit words, MSB first)
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printf("RESULT: %08X%08X%08X%08X%08X%08X%08X%08X\n",
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dut->data_o[7], dut->data_o[6], dut->data_o[5], dut->data_o[4],
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dut->data_o[3], dut->data_o[2], dut->data_o[1], dut->data_o[0]);
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dut->clk = 0; main_time += 5; dut->eval();
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}
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delete dut;
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return 0;
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}
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