FallenSigh
5941fee980
Phase 1 complete — all 4 leaf modules verified: - rng_sync.v: 256-bit Galois LFSR PRNG (10/10 PASS) - sample_cbd_sync.v: CBD sampler with keccak_core PRF (2560/2560 PASS) - sample_ntt_sync.v: SHAKE-128 rejection sampling for A matrix (1536/1536 PASS) - xsim Verilog TBs for sha3 module (tb_sha3_xsim.v, tb_sha3_xsim_simple.v, tb_keccak_core_xsim.v)
51 lines
1.3 KiB
Verilog
51 lines
1.3 KiB
Verilog
// rng_sync.v - 256-bit Galois LFSR PRNG (taps: 255,253,252,247,0)
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module rng_sync #(
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parameter [255:0] SEED = 256'hDEADBEEFCAFEBABEFEEDFACEDECAFBAD1234567887654321ABCDEF010FEDCBA9
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) (
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input clk,
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input rst_n,
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input valid_i,
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output ready_o,
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output [255:0] data_o,
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output valid_o,
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input ready_i
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);
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reg [255:0] state;
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reg valid_r;
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reg [255:0] lfsr_next;
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wire feedback;
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integer i;
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assign ready_o = 1'b1;
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assign valid_o = valid_r;
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assign data_o = state;
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assign feedback = state[0];
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always @(*) begin
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for (i = 0; i < 255; i = i + 1)
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lfsr_next[i] = state[i+1];
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lfsr_next[255] = feedback;
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lfsr_next[254] = lfsr_next[254] ^ feedback;
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lfsr_next[252] = lfsr_next[252] ^ feedback;
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lfsr_next[251] = lfsr_next[251] ^ feedback;
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lfsr_next[246] = lfsr_next[246] ^ feedback;
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= SEED;
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valid_r <= 1'b0;
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end else begin
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if (valid_r && ready_i)
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valid_r <= 1'b0;
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if (valid_i) begin
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state <= lfsr_next;
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valid_r <= 1'b1;
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end
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end
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end
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endmodule
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