FallenSigh
8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
7 lines
175 B
Systemverilog
7 lines
175 B
Systemverilog
`ifndef DEFINES_VH
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`define DEFINES_VH
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`define CLK_PERIOD 10.0 // 100MHz
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`define Q 3329 // ML-KEM prime modulus
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`define N 256 // polynomial degree
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`endif
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