FallenSigh
2f206a6bc5
Fresh valid/ready KeyGen FSM for ML-KEM-512 (K=2, eta1=3). Independent keccak per consumer (no arbiter). Verified stage-by-stage vs ml-kem-r golden: - 2a G(d||K): rho/sigma exact (d byte0-low, K at byte32, no reversal). - 2b SampleNTT: A_hat[i][j] from seed rho||j||i, 1024/1024 coeffs exact. - 2c CBD: s[i]=CBD3(PRF(sigma,i)), e[i]=CBD3(PRF(sigma,K+i)); signed->mod-q (+Q when negative); 2048/2048 (A+s+e) coeffs exact. polymem register array (10 slots x 256), debug readback tap (dbg_slot/idx -> coeff, rho/sigma taps) for stage TBs. a_busy/c_busy guards (defensive after sample_ntt fix). FSM: IDLE->G->A->C->DONE (datapath extended in later stages). Plan + progress doc in .claude/plans/keygen_plan.md.
278 lines
10 KiB
Verilog
278 lines
10 KiB
Verilog
// mlkem_top.v - ML-KEM-512 KeyGen top-level integration (K=2, eta1=3).
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//
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// Streaming valid/ready interface. Given seeds d and z, computes the
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// ML-KEM key pair per FIPS 203 Algorithm 16 (KeyGen_internal):
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// (rho,sigma) = G(d || K)
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// A_hat[i][j] = SampleNTT(rho || j || i) i,j in 0..K-1
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// s[i] = CBD3(PRF(sigma, i)), e[i] = CBD3(PRF(sigma, K+i))
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// s_hat[i] = NTT(s[i]); e_hat[i] = NTT(e[i])
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// t_hat[i] = e_hat[i] + sum_j A_hat[i][j] o s_hat[j]
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// ek = byteEncode12(t_hat[0..K-1]) || rho
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// dk = byteEncode12(s_hat[0..K-1]) || ek || H(ek) || z
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//
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// Built incrementally and verified stage-by-stage against ml-kem-r golden
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// vectors (test_framework/modules/mlkem_keygen/golden) and NIST KAT.
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//
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// Uses independent (verified) leaf modules, each with its own keccak_core:
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// sha3_top, sample_ntt_sync, sample_cbd_sync, ntt_core, poly_mul_sync,
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// mod_add_sync. No shared-keccak arbiter.
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`include "sync_rtl/common/defines.vh"
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module mlkem_top #(
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parameter K = 2, // ML-KEM-512
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parameter ETA1 = 3
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) (
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input clk,
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input rst_n,
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input [255:0] d_i, // KeyGen seed d (byte 0 in d_i[7:0])
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input [255:0] z_i, // implicit-rejection seed z
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input start_i, // pulse to begin KeyGen
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output busy_o, // high while running
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output done_o, // pulse when ek/dk ready
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// Debug readback tap: read one stored coefficient by (poly slot, index).
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// Lets stage TBs verify intermediates without wide buses.
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input [3:0] dbg_slot_i, // poly slot (see localparams below)
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input [7:0] dbg_idx_i, // coefficient index 0..255
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output [11:0] dbg_coeff_o,
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// Debug taps for hash outputs
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output [255:0] dbg_rho_o,
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output [255:0] dbg_sigma_o
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);
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localparam Q = `Q; // 3329
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// ================================================================
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// Polynomial storage: K=2 needs A_hat[2][2]=4, s/s_hat[2], e/e_hat[2],
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// t_hat[2]. Reuse slots: s and s_hat share (NTT in place), same for e.
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// Slot map:
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// 0..3 : A_hat[0][0],A_hat[0][1],A_hat[1][0],A_hat[1][1]
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// 4..5 : s_hat[0], s_hat[1] (s[i] then overwritten by NTT)
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// 6..7 : e_hat[0], e_hat[1] (e[i] then overwritten by NTT)
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// 8..9 : t_hat[0], t_hat[1]
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// ================================================================
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localparam SLOT_A00 = 4'd0, SLOT_A01 = 4'd1, SLOT_A10 = 4'd2, SLOT_A11 = 4'd3;
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localparam SLOT_S0 = 4'd4, SLOT_S1 = 4'd5;
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localparam SLOT_E0 = 4'd6, SLOT_E1 = 4'd7;
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localparam SLOT_T0 = 4'd8, SLOT_T1 = 4'd9;
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localparam NUM_SLOTS = 10;
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reg [11:0] polymem [0:NUM_SLOTS*256-1];
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// Debug readback (registered for timing)
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reg [11:0] dbg_coeff_r;
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always @(posedge clk) dbg_coeff_r <= polymem[dbg_slot_i*256 + dbg_idx_i];
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assign dbg_coeff_o = dbg_coeff_r;
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// ================================================================
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// Top-level FSM (built incrementally). Stage 2a: G only.
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// ================================================================
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localparam ST_IDLE = 4'd0;
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localparam ST_G = 4'd1; // run G(d||K), capture rho/sigma
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localparam ST_A = 4'd2; // generate A_hat[i][j] via SampleNTT
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localparam ST_C = 4'd3; // generate s[i],e[i] via CBD
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localparam ST_DONE = 4'd15;
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reg [3:0] st, st_next;
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reg [255:0] rho_r, sigma_r;
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// A-generation bookkeeping
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reg [2:0] a_pair; // 0..K*K (=4) pairs done
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reg [7:0] a_widx; // write index 0..255 within current poly
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reg a_busy; // 1 once current pair's request accepted (gates collect)
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wire [1:0] a_i = a_pair[1] ? 2'd1 : 2'd0; // pair/K (K=2)
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wire [1:0] a_j = a_pair[0] ? 2'd1 : 2'd0; // pair%K
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wire [3:0] a_slot = {2'b0, a_pair[1], a_pair[0]}; // SLOT_A00..A11 = pair index
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// C-generation bookkeeping: 2*K polys = s0,s1,e0,e1 (idx 0..3)
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reg [2:0] c_poly; // 0..2K
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reg [7:0] c_widx;
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reg c_busy; // 1 once current poly's request accepted (gates collect)
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wire [7:0] c_nonce = {5'b0, c_poly}; // s:0,1 e:2,3 == nonce
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// slot: c_poly 0->S0,1->S1,2->E0,3->E1
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wire [3:0] c_slot = (c_poly == 3'd0) ? SLOT_S0 :
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(c_poly == 3'd1) ? SLOT_S1 :
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(c_poly == 3'd2) ? SLOT_E0 : SLOT_E1;
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assign busy_o = (st != ST_IDLE);
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assign done_o = (st == ST_DONE);
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assign dbg_rho_o = rho_r;
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assign dbg_sigma_o = sigma_r;
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// ---- sha3_top in G mode: data_i = {K_byte, d} (d byte0 in [7:0]) ----
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reg sha3_valid;
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wire sha3_ready;
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wire [511:0] sha3_hash;
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wire sha3_vo;
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reg sha3_ack; // consumer ready for hash
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wire [511:0] g_data = {248'b0, 8'(K), d_i}; // data_i[263:256]=K, [255:0]=d
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sha3_top u_sha3 (
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.clk(clk), .rst_n(rst_n),
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.mode(2'b00), // G = SHA3-512
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.data_i(g_data),
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.valid_i(sha3_valid),
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.ready_o(sha3_ready),
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.hash_o(sha3_hash),
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.valid_o(sha3_vo),
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.ready_i(sha3_ack),
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.mb_en(1'b0), .mb_block_i(1088'b0), .mb_valid_i(1'b0),
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.mb_last_i(1'b0), .mb_ready_o()
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);
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// ---- sample_ntt_sync: Â[i][j] = SampleNTT(rho || j || i) ----
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reg snt_valid;
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wire snt_ready;
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wire [11:0] snt_coeff;
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wire snt_vo;
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wire snt_last;
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reg snt_ack; // we accept coeffs
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sample_ntt_sync #(.K(K)) u_snt (
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.clk(clk), .rst_n(rst_n),
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.rho_i(rho_r),
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.k_i(3'(K)),
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.i_idx(a_i),
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.j_idx(a_j),
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.valid_i(snt_valid),
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.ready_o(snt_ready),
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.coeff_o(snt_coeff),
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.valid_o(snt_vo),
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.ready_i(snt_ack),
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.last_o(snt_last)
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);
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// ---- sample_cbd_sync: s[i]=CBD3(PRF(sigma,i)), e[i]=CBD3(PRF(sigma,K+i)) ----
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reg cbd_valid;
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wire cbd_ready;
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wire [11:0] cbd_coeff; // 12-bit signed (two's complement)
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wire cbd_vo;
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wire cbd_last;
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reg cbd_ack;
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sample_cbd_sync u_cbd (
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.clk(clk), .rst_n(rst_n),
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.seed_i(sigma_r),
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.nonce_i(c_nonce),
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.eta_i(2'(ETA1)),
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.valid_i(cbd_valid),
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.ready_o(cbd_ready),
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.coeff_o(cbd_coeff),
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.valid_o(cbd_vo),
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.ready_i(cbd_ack),
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.last_o(cbd_last)
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);
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// signed (two's complement) -> [0,Q): add Q when negative
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wire [11:0] cbd_modq = cbd_coeff[11] ? (cbd_coeff + 12'(Q)) : cbd_coeff;
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always @(*) begin
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st_next = st;
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case (st)
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ST_IDLE: if (start_i) st_next = ST_G;
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ST_G: if (sha3_vo) st_next = ST_A;
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ST_A: if (a_pair >= K*K) st_next = ST_C;
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ST_C: if (c_poly >= 2*K) st_next = ST_DONE;
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ST_DONE: st_next = ST_IDLE;
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default: st_next = ST_IDLE;
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endcase
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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st <= ST_IDLE;
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rho_r <= 256'd0;
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sigma_r <= 256'd0;
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sha3_valid <= 1'b0;
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sha3_ack <= 1'b0;
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snt_valid <= 1'b0;
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snt_ack <= 1'b0;
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a_pair <= 3'd0;
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a_widx <= 8'd0;
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a_busy <= 1'b0;
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cbd_valid <= 1'b0;
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cbd_ack <= 1'b0;
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c_poly <= 3'd0;
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c_widx <= 8'd0;
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c_busy <= 1'b0;
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end else begin
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st <= st_next;
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// Kick off G when entering ST_G
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if (st == ST_IDLE && start_i) begin
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sha3_valid <= 1'b1;
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sha3_ack <= 1'b1;
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end
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// Drop valid once accepted
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if (sha3_valid && sha3_ready) sha3_valid <= 1'b0;
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// Capture rho/sigma when G completes; arm A stage
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if (st == ST_G && sha3_vo) begin
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rho_r <= sha3_hash[255:0]; // rho = G output bytes 0..31
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sigma_r <= sha3_hash[511:256]; // sigma = bytes 32..63
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sha3_ack <= 1'b0;
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snt_valid <= 1'b1; // start first SampleNTT
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snt_ack <= 1'b1;
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a_pair <= 3'd0;
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a_widx <= 8'd0;
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a_busy <= 1'b0;
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end
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// ---- ST_A: drive SampleNTT, store 256 coeffs per pair ----
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if (st == ST_A) begin
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// mark busy once this pair's request accepted
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if (snt_valid && snt_ready) begin
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snt_valid <= 1'b0;
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a_busy <= 1'b1;
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end
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// store each output coefficient only while busy (ignore stale last coeff from prior poly)
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if (a_busy && snt_vo && snt_ack) begin
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polymem[a_slot*256 + a_widx] <= snt_coeff;
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if (snt_last) begin
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// finished this poly; advance to next pair
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a_pair <= a_pair + 3'd1;
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a_widx <= 8'd0;
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a_busy <= 1'b0;
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// start next SampleNTT if more pairs remain
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if (a_pair + 3'd1 < K*K) snt_valid <= 1'b1;
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end else begin
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a_widx <= a_widx + 8'd1;
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end
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end
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end
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// Arm C stage when A finishes
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if (st == ST_A && st_next == ST_C) begin
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cbd_valid <= 1'b1;
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cbd_ack <= 1'b1;
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c_poly <= 3'd0;
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c_widx <= 8'd0;
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c_busy <= 1'b0;
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end
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// ---- ST_C: drive CBD, store 256 mod-q coeffs per poly ----
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if (st == ST_C) begin
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if (cbd_valid && cbd_ready) begin
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cbd_valid <= 1'b0;
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c_busy <= 1'b1;
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end
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if (c_busy && cbd_vo && cbd_ack) begin
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polymem[c_slot*256 + c_widx] <= cbd_modq;
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if (cbd_last) begin
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c_poly <= c_poly + 3'd1;
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c_widx <= 8'd0;
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c_busy <= 1'b0;
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if (c_poly + 3'd1 < 2*K) cbd_valid <= 1'b1;
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end else begin
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c_widx <= c_widx + 8'd1;
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end
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end
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end
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end
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end
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endmodule
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