FallenSigh
4997657d7e
Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now 120/120 vectors. Also ignore .omo/ session runtime cache and archive the 06-27-sha3-g-test-specific-input trellis task. Verified all 10 modules pass both frameworks: - Verilator: 4334/4334 vectors - XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203 Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).
2 lines
137 B
JSON
2 lines
137 B
JSON
{"file": ".trellis/spec/rtl/xsim-tb-conventions.md", "reason": "遵循 XSIM testbench 编写规范：时钟、复位、DUT驱动协议"}
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