FallenSigh
d4c3fc86fc
Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script
288 lines
12 KiB
Verilog
288 lines
12 KiB
Verilog
// tb_sha3_chain_xsim.v - Vivado xsim testbench for sha3_chain_top
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//
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// Tests the ML-KEM G function: SHA3-512(d_in || 0x02) → {rho, sigma}.
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// Uses $readmemh file-based test vectors for d_in values.
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//
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// Vector format (256 bits = 64 hex chars per line):
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// Each line is a 256-bit d_in value (MSB-first hex).
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//
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// Expected rho/sigma values are hardcoded (computed by gen_vectors.py
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// using hashlib.sha3_512).
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//
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// Protocol: start_i / done_o handshake
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// 1. Drive d_in, assert start_i=1
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// 2. Wait for done_o=1 (with timeout watchdog)
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// 3. Capture rho_out, sigma_out
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// 4. Compare with expected values
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// 5. Deassert start_i (FSM returns to IDLE)
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`timescale 1ns / 1ps
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module tb_sha3_chain_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter VECTOR_FILE = "sync_rtl/sha3_chain/TB/vectors/sha3_chain_input.hex";
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parameter RESULT_FILE = "sync_rtl/sha3_chain/TB/vectors/sha3_chain_result.hex";
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parameter MAX_VECTORS = 256;
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parameter TIMEOUT_CYCLES = 2000;
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// ================================================================
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// DUT signals
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// ================================================================
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reg clk;
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reg rst_n;
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reg [255:0] d_in;
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reg start_i;
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wire done_o;
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wire [255:0] rho_out;
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wire [255:0] sigma_out;
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// ================================================================
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// Expected values (computed by gen_vectors.py)
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// 8 test vectors total
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// ================================================================
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reg [255:0] expected_rho [0:7];
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reg [255:0] expected_sigma [0:7];
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initial begin
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// all-zeros
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expected_rho[0] = 256'h6a0af64a85e909df8e2816605d20b4e382b30bbb61bf3a5f821a0b5dba9ad3e7;
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expected_sigma[0] = 256'he367d3e9ab3b86b64230aa8bf8815d408ef819f9e9d956ce22bbc2f68eaa9e3a;
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// all-ones
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expected_rho[1] = 256'hf393670510fe33b5df9efb515bf1515c84bdf625e3c53154c10c7d2c92b7f234;
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expected_sigma[1] = 256'h9fac853f1e61e8389a04fc710845963c18e48fbec11c66d7d6567f8e168160cc;
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// lsb-one
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expected_rho[2] = 256'h90ad3aafcc6bde61dc5014cf6cdee8065504733fc0caa8bddf3e1689a7b7b302;
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expected_sigma[2] = 256'h3c8686e00e96619b07c7d56fa1effce7ec5597f94a9109ec40c2a6314f6e4ada;
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// msb-one
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expected_rho[3] = 256'h6c914803c353f4f3b4d8cc541b67019dd2d04cd0fb2ba51b8ebaba973d8f5cbe;
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expected_sigma[3] = 256'h33d64b904e1afa541dbe72162021b54c7aef182125da38d88dd7d076636af6cf;
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// pattern-aa
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expected_rho[4] = 256'h561a98ff76434dc201ca8152cf2b97342090157a522354e299db35fec29690aa;
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expected_sigma[4] = 256'hed57f5826ed6e77c756cf821244b350e6b34eb05f9639e227f9a5e130eca649f;
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// pattern-55
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expected_rho[5] = 256'hff31fe4fc62849226d9197992b1a2d0429c2c325011d2c7bb48860920c04636c;
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expected_sigma[5] = 256'hdb5f9599ae43d39fa182896d0ab1d1af663f19355dfeb951fed7b1c8c94eb0d3;
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// random-1
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expected_rho[6] = 256'h4538916fc357ba9fe24033fa8c1e18cbfb14faf7e1771e0d7521c80cb0d4379f;
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expected_sigma[6] = 256'h78565d212000aabb8086e3373ad82d45c07589bcca35409a3f5d9fd30623340e;
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// random-2
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expected_rho[7] = 256'h176c0b7e91b90ae50757b14bbec130a9e328d09d020466565829de47f6b387cd;
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expected_sigma[7] = 256'h413f41c838828e079d5e06b06de61eed6b5bd5005b334e516be6e3b900da7938;
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end
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// ================================================================
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// DUT instantiation
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// ================================================================
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sha3_chain_top u_dut (
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.clk (clk),
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.rst_n (rst_n),
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.d_in (d_in),
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.start_i (start_i),
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.done_o (done_o),
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.rho_out (rho_out),
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.sigma_out(sigma_out)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// ================================================================
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reg [255:0] vector_mem [0:MAX_VECTORS-1];
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer result_fd;
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integer pass_count;
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integer fail_count;
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// ================================================================
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// Hex-to-ASCII conversion helper
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// ================================================================
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function [7:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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if (nibble < 4'd10)
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nibble_to_ascii = 8'h30 + {4'd0, nibble};
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else
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nibble_to_ascii = 8'h41 + ({4'd0, nibble} - 4'd10);
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end
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endfunction
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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vec_count = 0;
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$readmemh(VECTOR_FILE, vector_mem);
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// Count non-X entries
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (vector_mem[idx] === 256'hx || vector_mem[idx] === 256'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists.");
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$display(" Format: 64 hex chars per line (256-bit d_in)");
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Open result file
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result_fd = $fopen(RESULT_FILE, "w");
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if (result_fd == 0) begin
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$display("ERROR: Cannot open result file: %s", RESULT_FILE);
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$finish;
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end
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// Initialize DUT inputs
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d_in <= 256'd0;
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start_i <= 1'b0;
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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begin
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reg [255:0] vec_d_in;
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reg [255:0] captured_rho;
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reg [255:0] captured_sigma;
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integer bit_idx;
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reg [3:0] nib;
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vec_d_in = vector_mem[idx];
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$display("INFO: Vector %0d - d_in=0x%064h", idx, vec_d_in);
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// Drive d_in and assert start_i
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d_in <= vec_d_in;
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start_i <= 1'b1;
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@(posedge clk);
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// Wait for done_o (with timeout)
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cycle_count = 0;
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while (!done_o && cycle_count < TIMEOUT_CYCLES) begin
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@(posedge clk);
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cycle_count = cycle_count + 1;
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end
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if (cycle_count >= TIMEOUT_CYCLES) begin
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$display("ERROR: Timeout waiting for done_o on vector %0d", idx);
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$fwrite(result_fd, "TIMEOUT: vector %0d d_in=0x%064h\n", idx, vec_d_in);
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fail_count = fail_count + 1;
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// Force reset the FSM
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start_i <= 1'b0;
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@(posedge clk);
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end else begin
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// Capture outputs (valid on cycle done_o=1)
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captured_rho = rho_out;
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captured_sigma = sigma_out;
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// Deassert start_i (FSM returns to IDLE on next cycle)
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start_i <= 1'b0;
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// Check rho
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if (captured_rho !== expected_rho[idx]) begin
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$display("FAIL: Vector %0d RHO mismatch", idx);
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$display(" expected = 0x%064h", expected_rho[idx]);
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$display(" got = 0x%064h", captured_rho);
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$fwrite(result_fd, "FAIL: vector %0d RHO expected=0x%064h got=0x%064h\n",
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idx, expected_rho[idx], captured_rho);
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fail_count = fail_count + 1;
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end else begin
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pass_count = pass_count + 1;
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end
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// Check sigma
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if (captured_sigma !== expected_sigma[idx]) begin
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$display("FAIL: Vector %0d SIGMA mismatch", idx);
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$display(" expected = 0x%064h", expected_sigma[idx]);
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$display(" got = 0x%064h", captured_sigma);
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$fwrite(result_fd, "FAIL: vector %0d SIGMA expected=0x%064h got=0x%064h\n",
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idx, expected_sigma[idx], captured_sigma);
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fail_count = fail_count + 1;
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end else begin
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pass_count = pass_count + 1;
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end
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// Write results to output file
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$fwrite(result_fd, "RESULT: %0d ", idx);
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$fwrite(result_fd, "d_in=0x");
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for (bit_idx = 63; bit_idx >= 0; bit_idx = bit_idx - 1) begin
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nib = vec_d_in[(bit_idx*4)+:4];
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$fwrite(result_fd, "%c", nibble_to_ascii(nib));
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end
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$fwrite(result_fd, " rho=0x");
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for (bit_idx = 63; bit_idx >= 0; bit_idx = bit_idx - 1) begin
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nib = captured_rho[(bit_idx*4)+:4];
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$fwrite(result_fd, "%c", nibble_to_ascii(nib));
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end
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$fwrite(result_fd, " sigma=0x");
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for (bit_idx = 63; bit_idx >= 0; bit_idx = bit_idx - 1) begin
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nib = captured_sigma[(bit_idx*4)+:4];
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$fwrite(result_fd, "%c", nibble_to_ascii(nib));
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end
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$fwrite(result_fd, "\n");
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@(posedge clk);
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end
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end // inner begin block
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end
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// ============================================================
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// Summary
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// ============================================================
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$fclose(result_fd);
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$display("========================================");
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$display("SHA3 CHAIN TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Checks (rho+sigma): %0d", vec_count * 2);
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display(" Results written to: %s", RESULT_FILE);
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if (fail_count == 0)
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$display(" RESULT: ALL TESTS PASSED");
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else
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$display(" RESULT: SOME TESTS FAILED");
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$display("========================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog
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// ================================================================
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initial begin
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#(TIMEOUT_CYCLES * 10 * 100);
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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