FallenSigh
a369a421b7
Phase 3.1 + 3.3: - sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM) - s_bram.v: single-port RAM (rd_en/wr_en, write priority) - comp_decomp_sync.v: streaming compress/decompress with round-half-up Verified: storage 5/5, comp_decomp 60/60 all PASS
18 lines
416 B
JSON
18 lines
416 B
JSON
{
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"module": "storage",
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"rtl_top": "sync_rtl/storage/sd_bram.v",
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"rtl_deps": ["sync_rtl/storage/s_bram.v"],
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"tb_cpp": "sync_rtl/storage/TB/tb_storage.cpp",
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"simulator": "verilator",
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"timeout_s": 30,
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"cases": [
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{
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"id": "rw_test",
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"description": "Write-read test for sd_bram (s_bram compiled as dep)",
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"params": {},
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"num_vectors": 5,
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"tolerance": "bit_exact"
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}
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]
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}
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