FallenSigh
5941fee980
Phase 1 complete — all 4 leaf modules verified: - rng_sync.v: 256-bit Galois LFSR PRNG (10/10 PASS) - sample_cbd_sync.v: CBD sampler with keccak_core PRF (2560/2560 PASS) - sample_ntt_sync.v: SHAKE-128 rejection sampling for A matrix (1536/1536 PASS) - xsim Verilog TBs for sha3 module (tb_sha3_xsim.v, tb_sha3_xsim_simple.v, tb_keccak_core_xsim.v)
113 lines
3.7 KiB
Python
113 lines
3.7 KiB
Python
"""gen_vectors.py - Test vector generator for rng module.
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Generates expected 256-bit LFSR output values using the same Galois LFSR
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polynomial as the RTL: x^256 + x^255 + x^253 + x^252 + x^247 + 1
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Taps: [255, 253, 252, 247, 0]
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"""
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import os
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import sys
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# Add test_framework/lib to path for VectorGenerator base class
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sys.path.insert(0, os.path.join(os.path.dirname(__file__), '..', '..', 'lib'))
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from vector_gen import VectorGenerator
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# Default seed matches RTL SEED parameter
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DEFAULT_SEED = 0xDEADBEEFCAFEBABEFEEDFACEDECAFBAD1234567887654321ABCDEF010FEDCBA9
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# 256-bit mask
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MASK_256 = (1 << 256) - 1
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class _LFSR256:
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"""256-bit Galois LFSR matching rng_sync.v implementation.
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Polynomial: x^256 + x^255 + x^253 + x^252 + x^247 + 1
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Taps: [255, 253, 252, 247, 0]
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"""
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def __init__(self, seed: int):
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self.state = seed & MASK_256
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def next(self) -> int:
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"""Advance LFSR one step and return the new state."""
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feedback = self.state & 1 # LSB = state[0]
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# Shift right by 1, feedback into MSB (position 255)
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new_state = (self.state >> 1) | (feedback << 255)
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# XOR feedback into tap positions (shifted)
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if feedback:
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new_state ^= (1 << 254) # tap 255 -> position 254
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new_state ^= (1 << 252) # tap 253 -> position 252
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new_state ^= (1 << 251) # tap 252 -> position 251
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new_state ^= (1 << 246) # tap 247 -> position 246
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self.state = new_state & MASK_256
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return self.state
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class RngVectorGenerator(VectorGenerator):
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"""Generates test vectors for the rng_sync module."""
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def __init__(self):
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super().__init__()
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self._lfsr = None
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def _ensure_lfsr(self, params: dict) -> None:
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"""Initialize LFSR on first call or when params change seed."""
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seed = params.get('seed', DEFAULT_SEED)
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if self._lfsr is None:
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self._lfsr = _LFSR256(seed)
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def generate_one(self, params: dict) -> dict:
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"""Generate one LFSR output value.
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On each call, advances the LFSR from its current state and returns
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the new state. This matches the RTL behavior: valid_i advances the
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LFSR, and the new value appears on data_o.
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Args:
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params: Optional dict with 'seed' key to override default seed.
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Returns:
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dict with 'input' (empty) and 'expected' {'data': lfsr_state_hex}.
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"""
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self._ensure_lfsr(params)
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new_state = self._lfsr.next()
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return {
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'input': {},
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'expected': {'data': new_state}
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}
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def write_hex_file(self, vectors: list[dict], filepath: str) -> None:
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"""Write input file with one dummy line per vector.
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The RNG has no input signals, but the testbench reads the hex file
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to determine the number of vectors to generate. Each line acts as
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a pulse trigger.
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Args:
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vectors: List of vector dicts from generate_one().
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filepath: Path to write the hex file.
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"""
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os.makedirs(os.path.dirname(filepath), exist_ok=True)
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with open(filepath, 'w') as f:
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for _ in vectors:
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f.write('0\n')
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def write_expected_file(self, vectors: list[dict], filepath: str) -> None:
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"""Write expected output as 64-char hex strings, one per line.
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Args:
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vectors: List of vector dicts from generate_one().
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filepath: Path to write the expected hex file.
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"""
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os.makedirs(os.path.dirname(filepath), exist_ok=True)
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with open(filepath, 'w') as f:
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for v in vectors:
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data = v['expected']['data']
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# Format as 64-character uppercase hex string
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f.write(f'{data:064X}\n')
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