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8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
18 lines
437 B
JSON
18 lines
437 B
JSON
{
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"module": "mod_add",
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"rtl_top": "sync_rtl/mod_add/mod_add_sync.v",
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"rtl_deps": ["sync_rtl/common/pipeline_reg.v"],
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"tb_cpp": "sync_rtl/mod_add/TB/tb_mod_add.cpp",
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"simulator": "verilator",
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"timeout_s": 30,
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"cases": [
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{
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"id": "basic",
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"description": "Random (a+b) mod Q pairs, no overflow, with overflow, edge cases",
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"params": {},
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"num_vectors": 50,
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"tolerance": "bit_exact"
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}
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]
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}
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