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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
122 lines
3.6 KiB
Python
122 lines
3.6 KiB
Python
"""gen_vectors.py - Test vector generator for mod_add module.
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Generates (a, b) input pairs and computes expected (a + b) mod Q.
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"""
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import os
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import random
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import sys
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# Add test_framework/lib to path for VectorGenerator base class
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sys.path.insert(0, os.path.join(os.path.dirname(__file__), '..', '..', 'lib'))
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from vector_gen import VectorGenerator
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Q = 3329 # ML-KEM prime modulus
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class ModAddVectorGenerator(VectorGenerator):
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"""Generates test vectors for the mod_add_sync module."""
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def generate_one(self, params: dict) -> dict:
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"""Generate a single (a, b) pair with expected modular sum.
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Uses random values covering:
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- No overflow: a + b < Q
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- With overflow: a + b >= Q
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- Edge cases: a=0, b=0, a=Q-1, b=Q-1
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Args:
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params: Unused for mod_add basic case.
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Returns:
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dict with 'input' and 'expected' keys.
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"""
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# Mix of random and edge cases for coverage
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roll = random.random()
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if roll < 0.05:
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# Both zero
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a, b = 0, 0
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elif roll < 0.10:
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# a=0, b random
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a = 0
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b = random.randint(0, Q - 1)
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elif roll < 0.15:
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# b=0, a random
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a = random.randint(0, Q - 1)
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b = 0
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elif roll < 0.20:
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# Both Q-1 (max overflow)
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a, b = Q - 1, Q - 1
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elif roll < 0.25:
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# a random, b = Q-1
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a = random.randint(0, Q - 1)
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b = Q - 1
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elif roll < 0.65:
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# No overflow: both small
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a = random.randint(0, Q // 2 - 1)
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b = random.randint(0, Q // 2 - 1)
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else:
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# Potential overflow
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a = random.randint(0, Q - 1)
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b = random.randint(0, Q - 1)
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# Compute expected: (a + b) mod Q
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expected_sum = (a + b) % Q
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return {
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'input': {'a': a, 'b': b},
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'expected': {'sum': expected_sum}
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}
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def write_hex_file(self, vectors: list[dict], filepath: str) -> None:
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"""Write input vectors as "AAA BBB" hex format.
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Args:
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vectors: List of vector dicts from generate_one().
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filepath: Path to write the hex file.
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"""
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os.makedirs(os.path.dirname(filepath), exist_ok=True)
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with open(filepath, 'w') as f:
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for v in vectors:
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a = v['input']['a']
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b = v['input']['b']
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f.write(f'{a:03X} {b:03X}\n')
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def write_expected_file(self, vectors: list[dict], filepath: str) -> None:
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"""Write expected output as "CCC" hex format.
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Args:
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vectors: List of vector dicts from generate_one().
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filepath: Path to write the expected hex file.
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"""
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os.makedirs(os.path.dirname(filepath), exist_ok=True)
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with open(filepath, 'w') as f:
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for v in vectors:
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s = v['expected']['sum']
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f.write(f'{s:03X}\n')
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def compare_results(self, got: list[str], expected_file: str) -> bool:
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"""Compare RTL output against expected values.
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Args:
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got: List of hex result strings from simulation.
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expected_file: Path to expected hex file.
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Returns:
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bool: True if all results match.
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"""
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with open(expected_file, 'r') as f:
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expected = [line.strip() for line in f
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if line.strip() and not line.startswith('#')]
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if len(got) != len(expected):
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return False
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for i, (g, e) in enumerate(zip(got, expected)):
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if g.upper() != e.upper():
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return False
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return True
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