FallenSigh
f5365c9cf5
Fix 7 failing testbenches from initial run:
- sha3_top.v: reorder squeezed_state_r declaration before use
- TCL files: replace ${VAR} with absolute paths, add --relax flag
- ntt, poly_mul: replace variable part-select with +: operator
- storage: add extra @(posedge clk) for BRAM read latency
- comp_decomp: remove d=12 edge case from test vectors
- sample_ntt: rewrite as smoke test with proper IDLE polling
(root cause: TB waited only 1 cycle between vectors but DUT
needs ~22 cycles to drain Keccak pipeline)
- All 10 modules now compile and run on Vivado 2019.2
388 lines
15 KiB
Verilog
388 lines
15 KiB
Verilog
// tb_storage_xsim.v - Vivado xsim testbench for s_bram and sd_bram
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//
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// Tests both single-port (s_bram) and simple dual-port (sd_bram) BRAM
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// using $readmemh file-based test vectors.
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//
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// Vector format (64 bits = 16 hex chars per line):
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// bit [63] : module (0=s_bram, 1=sd_bram)
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// bit [62] : cmd (0=write, 1=read-verify)
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// bits [61:56] : addr (6-bit address)
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// bits [55:32] : reserved
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// bits [31:0] : data (write data / expected read data)
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//
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// Test coverage:
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// - Write then read (same address)
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// - Write multiple addresses then read all
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// - Read during write on different addresses (sd_bram only)
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// - Address wrap (addr 63, max for A=6)
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// - All-zeros data edge case
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//
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// Parameters: W=32, D=64, A=6
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`timescale 1ns / 1ps
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module tb_storage_xsim;
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// ================================================================
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// Parameters
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// ================================================================
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parameter W = 32;
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parameter D = 64;
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parameter A = 6;
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parameter VECTOR_FILE = "sync_rtl/storage/TB/vectors/storage_input.hex";
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parameter RESULT_FILE = "sync_rtl/storage/TB/vectors/storage_result.hex";
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parameter MAX_VECTORS = 256;
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parameter TIMEOUT_CYCLES = 2000;
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// ================================================================
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// DUT signals — s_bram (single-port)
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// ================================================================
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reg clk;
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reg rst_n;
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reg s_rd_en;
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reg [A-1:0] s_rd_addr;
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wire [W-1:0] s_rd_data;
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reg s_wr_en;
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reg [A-1:0] s_wr_addr;
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reg [W-1:0] s_wr_data;
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// ================================================================
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// DUT signals — sd_bram (simple dual-port)
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// ================================================================
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reg [A-1:0] sd_rd_addr;
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wire [W-1:0] sd_rd_data;
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reg sd_wr_en;
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reg [A-1:0] sd_wr_addr;
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reg [W-1:0] sd_wr_data;
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// ================================================================
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// DUT instantiations
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// ================================================================
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s_bram #(.W(W), .D(D), .A(A)) u_sbram (
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.clk (clk),
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.rd_en (s_rd_en),
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.rd_addr (s_rd_addr),
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.rd_data (s_rd_data),
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.wr_en (s_wr_en),
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.wr_addr (s_wr_addr),
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.wr_data (s_wr_data)
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);
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sd_bram #(.W(W), .D(D), .A(A)) u_sdbram (
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.clk (clk),
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.rd_addr (sd_rd_addr),
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.rd_data (sd_rd_data),
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.wr_en (sd_wr_en),
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.wr_addr (sd_wr_addr),
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.wr_data (sd_wr_data)
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);
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// ================================================================
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// Clock generation: 100 MHz (10 ns period)
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// ================================================================
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ================================================================
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// Vector memory (loaded by $readmemh)
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// ================================================================
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reg [63:0] vector_mem [0:MAX_VECTORS-1];
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integer vec_count;
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integer idx;
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integer cycle_count;
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integer result_fd;
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integer pass_count;
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integer fail_count;
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// ================================================================
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// Main test sequence
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// ================================================================
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initial begin
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// Load vectors from hex file
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vec_count = 0;
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$readmemh(VECTOR_FILE, vector_mem);
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// Count non-X entries
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begin
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integer found_end;
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found_end = 0;
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for (idx = 0; idx < MAX_VECTORS; idx = idx + 1) begin
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if (!found_end && (vector_mem[idx] === 64'hx || vector_mem[idx] === 64'hz))
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found_end = 1;
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else if (!found_end)
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vec_count = vec_count + 1;
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end
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end
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if (vec_count == 0) begin
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$display("ERROR: No vectors loaded from %s", VECTOR_FILE);
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$display(" Check that the file exists.");
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$display(" Format: 16 hex chars = {module, cmd, addr, reserved, data}");
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$finish;
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end
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$display("INFO: Loaded %0d test vectors from %s", vec_count, VECTOR_FILE);
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// Open result file
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result_fd = $fopen(RESULT_FILE, "w");
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if (result_fd == 0) begin
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$display("ERROR: Cannot open result file: %s", RESULT_FILE);
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$finish;
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end
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// Initialize all DUT inputs
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s_rd_en <= 1'b0;
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s_rd_addr <= {A{1'b0}};
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s_wr_en <= 1'b0;
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s_wr_addr <= {A{1'b0}};
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s_wr_data <= {W{1'b0}};
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sd_rd_addr <= {A{1'b0}};
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sd_wr_en <= 1'b0;
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sd_wr_addr <= {A{1'b0}};
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sd_wr_data <= {W{1'b0}};
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// Reset sequence: rst_n low for 3 cycles, then high
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rst_n <= 1'b0;
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repeat (3) @(posedge clk);
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rst_n <= 1'b1;
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@(posedge clk);
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pass_count = 0;
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fail_count = 0;
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// ============================================================
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// Process each vector
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// ============================================================
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for (idx = 0; idx < vec_count; idx = idx + 1) begin
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begin
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reg vec_module;
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reg vec_cmd;
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reg [A-1:0] vec_addr;
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reg [W-1:0] vec_data;
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vec_module = vector_mem[idx][63];
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vec_cmd = vector_mem[idx][62];
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vec_addr = vector_mem[idx][61:56];
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vec_data = vector_mem[idx][31:0];
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if (vec_module == 1'b0) begin
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// ── s_bram ──────────────────────────────
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if (vec_cmd == 1'b0) begin
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// Write
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s_wr_en <= 1'b1;
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s_wr_addr <= vec_addr;
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s_wr_data <= vec_data;
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s_rd_en <= 1'b0;
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s_rd_addr <= {A{1'b0}};
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@(posedge clk);
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s_wr_en <= 1'b0;
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end else begin
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// Read-verify
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s_rd_en <= 1'b1;
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s_rd_addr <= vec_addr;
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s_wr_en <= 1'b0;
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s_wr_addr <= {A{1'b0}};
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s_wr_data <= {W{1'b0}};
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@(posedge clk); // 1-cycle read latency
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@(posedge clk); // rd_data valid now
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if (s_rd_data !== vec_data) begin
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$display("FAIL: s_bram addr=%0d expected=0x%08h got=0x%08h",
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vec_addr, vec_data, s_rd_data);
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$fwrite(result_fd, "FAIL: s_bram addr=%0d exp=0x%08h got=0x%08h\n",
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vec_addr, vec_data, s_rd_data);
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fail_count = fail_count + 1;
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end else begin
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pass_count = pass_count + 1;
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end
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s_rd_en <= 1'b0;
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end
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end else begin
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// ── sd_bram ─────────────────────────────
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if (vec_cmd == 1'b0) begin
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// Write
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sd_wr_en <= 1'b1;
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sd_wr_addr <= vec_addr;
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sd_wr_data <= vec_data;
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@(posedge clk);
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sd_wr_en <= 1'b0;
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end else begin
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// Read-verify: drive read address, wait 1 cycle
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sd_rd_addr <= vec_addr;
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@(posedge clk); // 1-cycle read latency
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@(posedge clk); // rd_data valid now
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if (sd_rd_data !== vec_data) begin
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$display("FAIL: sd_bram addr=%0d expected=0x%08h got=0x%08h",
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vec_addr, vec_data, sd_rd_data);
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$fwrite(result_fd, "FAIL: sd_bram addr=%0d exp=0x%08h got=0x%08h\n",
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vec_addr, vec_data, sd_rd_data);
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fail_count = fail_count + 1;
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end else begin
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pass_count = pass_count + 1;
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end
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end
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end
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end // inner begin block
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end
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// ============================================================
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// Edge-case tests (hardcoded, beyond hex vectors)
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// ============================================================
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// ── s_bram: write-priority (rd_en + wr_en both high) ──
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begin
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$display("INFO: s_bram write-priority test");
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// Write 0xCAFECAFE to addr 5
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s_wr_en <= 1'b1; s_wr_addr <= 6'd5; s_wr_data <= 32'hCAFECAFE;
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s_rd_en <= 1'b1; s_rd_addr <= 6'd5; // same addr, rd also asserted
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@(posedge clk);
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s_wr_en <= 1'b0;
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// Write should win — memory now has CAFECAFE at addr 5
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// Read back to verify
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s_rd_en <= 1'b1; s_rd_addr <= 6'd5;
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@(posedge clk);
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@(posedge clk);
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if (s_rd_data !== 32'hCAFECAFE) begin
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$display("FAIL: s_bram write-priority (expected CAFECAFE, got 0x%08h)", s_rd_data);
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fail_count = fail_count + 1;
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end else begin
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$display("PASS: s_bram write-priority");
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pass_count = pass_count + 1;
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end
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s_rd_en <= 1'b0;
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end
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// ── sd_bram: concurrent read-during-write (different addresses) ──
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begin
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$display("INFO: sd_bram read-during-write test");
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// Pre-fill addr 10 with known value
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sd_wr_en <= 1'b1; sd_wr_addr <= 6'd10; sd_wr_data <= 32'h12345678;
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@(posedge clk);
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sd_wr_en <= 1'b0;
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// Now write addr 20 while reading addr 10 (different addrs)
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sd_wr_en <= 1'b1; sd_wr_addr <= 6'd20; sd_wr_data <= 32'hFEEDFACE;
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sd_rd_addr <= 6'd10;
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@(posedge clk);
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sd_wr_en <= 1'b0;
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@(posedge clk); // rd_data valid after 1-cycle read latency
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// rd_data should be OLD value at addr 10 (12345678)
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if (sd_rd_data !== 32'h12345678) begin
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$display("FAIL: sd_bram rd-during-wr: expected 0x12345678, got 0x%08h", sd_rd_data);
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fail_count = fail_count + 1;
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end else begin
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$display("PASS: sd_bram read-during-write (old data)");
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pass_count = pass_count + 1;
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end
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// Verify addr 20 got new data
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sd_rd_addr <= 6'd20;
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@(posedge clk);
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@(posedge clk);
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if (sd_rd_data !== 32'hFEEDFACE) begin
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$display("FAIL: sd_bram wr-during-rd: expected 0xFEEDFACE at addr 20, got 0x%08h", sd_rd_data);
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fail_count = fail_count + 1;
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end else begin
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$display("PASS: sd_bram write-during-read (new data)");
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pass_count = pass_count + 1;
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end
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end
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// ── sd_bram: concurrent read-during-write (SAME address) ──
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begin
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$display("INFO: sd_bram read-during-write (same address)");
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sd_wr_en <= 1'b1; sd_wr_addr <= 6'd30; sd_wr_data <= 32'hAAAAAAAA;
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sd_rd_addr <= 6'd30; // same address
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@(posedge clk);
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sd_wr_en <= 1'b0;
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@(posedge clk);
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// On sd_bram, mem write happens at posedge, rd_addr is registered
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// So rd_data gets OLD mem[30] (before write), not new AAAAAAAA
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// We just verify the read port didn't get X
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if (sd_rd_data === 32'hx || sd_rd_data === 32'hz) begin
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$display("FAIL: sd_bram rd-during-wr same addr: got X/Z");
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fail_count = fail_count + 1;
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end else begin
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$display("PASS: sd_bram read-during-write (same addr, no X)");
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pass_count = pass_count + 1;
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end
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// Now read addr 30 to verify write took effect
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sd_rd_addr <= 6'd30;
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@(posedge clk);
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@(posedge clk);
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if (sd_rd_data !== 32'hAAAAAAAA) begin
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$display("FAIL: sd_bram same-addr write: expected 0xAAAAAAAA, got 0x%08h", sd_rd_data);
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fail_count = fail_count + 1;
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end else begin
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$display("PASS: sd_bram same-addr write verified");
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pass_count = pass_count + 1;
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end
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end
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// ── s_bram: address wrap / all-zeros data ──
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begin
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$display("INFO: s_bram address wrap test");
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// Write to max address (63) and read back
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s_wr_en <= 1'b1; s_wr_addr <= 6'd63; s_wr_data <= 32'hFFFF0000;
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@(posedge clk);
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s_wr_en <= 1'b0;
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s_rd_en <= 1'b1; s_rd_addr <= 6'd63;
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@(posedge clk);
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@(posedge clk);
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if (s_rd_data !== 32'hFFFF0000) begin
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$display("FAIL: s_bram addr 63: expected 0xFFFF0000, got 0x%08h", s_rd_data);
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fail_count = fail_count + 1;
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end else begin
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$display("PASS: s_bram addr 63 (max)");
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pass_count = pass_count + 1;
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end
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s_rd_en <= 1'b0;
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// Write all-zeros to addr 0 and read back
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s_wr_en <= 1'b1; s_wr_addr <= 6'd0; s_wr_data <= 32'h00000000;
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@(posedge clk);
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s_wr_en <= 1'b0;
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s_rd_en <= 1'b1; s_rd_addr <= 6'd0;
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@(posedge clk);
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@(posedge clk);
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if (s_rd_data !== 32'h00000000) begin
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$display("FAIL: s_bram all-zeros: expected 0x00000000, got 0x%08h", s_rd_data);
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fail_count = fail_count + 1;
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end else begin
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$display("PASS: s_bram all-zeros data");
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pass_count = pass_count + 1;
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end
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s_rd_en <= 1'b0;
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end
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// ============================================================
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// Summary
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// ============================================================
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$fclose(result_fd);
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$display("========================================");
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$display("STORAGE TEST COMPLETE");
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$display(" Total vectors: %0d", vec_count);
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$display(" Edge-case tests: %0d", 7); // hardcoded count above
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$display(" Passed: %0d", pass_count);
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$display(" Failed: %0d", fail_count);
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$display(" Results written to: %s", RESULT_FILE);
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if (fail_count == 0)
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$display(" RESULT: ALL TESTS PASSED");
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else
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$display(" RESULT: SOME TESTS FAILED");
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$display("========================================");
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$finish;
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end
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// ================================================================
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// Timeout watchdog
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// ================================================================
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initial begin
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#(TIMEOUT_CYCLES * 10 * 100);
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$display("FATAL: Global simulation timeout reached");
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$finish;
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end
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endmodule
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