// sha3_chain_top.v - Simple integration module: d → SHA3_G(d||k=2)
//
// Feeds external 256-bit d to sha3_top in G mode with k=2, captures
// rho (first 256 bits) and sigma (next 256 bits) from the hash output.
//
// 3-state FSM: IDLE → BUSY → DONE
//
// Interface:
//   clk, rst_n - clock, active-low reset
//   d_in[255:0] - 256-bit d input (external, NOT from RNG)
//   start_i     - start computation
//   done_o      - computation complete
//   rho_out     - G output first 256 bits
//   sigma_out   - G output next 256 bits

module sha3_chain_top (
    input              clk,
    input              rst_n,
    input  [255:0]     d_in,
    input              start_i,
    output             done_o,
    output [255:0]     rho_out,
    output [255:0]     sigma_out
);

    localparam ST_IDLE = 2'd0;
    localparam ST_BUSY = 2'd1;
    localparam ST_DONE = 2'd2;

    reg  [1:0]   state_r, state_next;

    // ── sha3_top signals ──
    wire [511:0]  sha3_data_i;
    wire          sha3_valid_i;
    wire          sha3_ready_o;
    wire [511:0]  sha3_hash_o;
    wire          sha3_valid_o;

    // data_i = {248'b0, k=8'd2, d_in}
    assign sha3_data_i = {248'b0, 8'd2, d_in};

    sha3_top u_sha3 (
        .clk      (clk),
        .rst_n    (rst_n),
        .mode     (2'b00),          // G mode (SHA3-512)
        .data_i   (sha3_data_i),
        .valid_i  (sha3_valid_i),
        .ready_o  (sha3_ready_o),
        .hash_o   (sha3_hash_o),
        .valid_o  (sha3_valid_o),
        .ready_i  (1'b1)            // always accept output
    );

    // valid_i: assert when IDLE + start_i + sha3 ready
    assign sha3_valid_i = (state_r == ST_IDLE) && start_i && sha3_ready_o;

    // done_o
    assign done_o = (state_r == ST_DONE);

    // ── output registers ──
    reg [255:0] rho_out_r, sigma_out_r;
    assign rho_out   = rho_out_r;
    assign sigma_out = sigma_out_r;

    // ── FSM combinational next-state ──
    always @(*) begin
        state_next = state_r;
        case (state_r)
            ST_IDLE: if (start_i && sha3_ready_o) state_next = ST_BUSY;
            ST_BUSY: if (sha3_valid_o)         state_next = ST_DONE;
            ST_DONE: if (!start_i)             state_next = ST_IDLE;
            default:                           state_next = ST_IDLE;
        endcase
    end

    // ── sequential logic ──
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state_r    <= ST_IDLE;
            rho_out_r   <= 256'd0;
            sigma_out_r <= 256'd0;
        end else begin
            state_r <= state_next;

            // Capture output when BUSY → DONE
            if (state_r == ST_BUSY && sha3_valid_o) begin
                rho_out_r   <= sha3_hash_o[255:0];
                sigma_out_r <= sha3_hash_o[511:256];
            end
        end
    end

endmodule