set PROJECT_DIR [file normalize [file dirname [info script]]] set REPORT_DIR ${PROJECT_DIR}/reports file mkdir ${REPORT_DIR} set PART xc7a200tfbg676-1 read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_round.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_core.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/sha3_top_shared.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_ntt/sample_ntt_sync_shared.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_cbd/sample_cbd_sync_shared.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/barrett_mul.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/barrett_mul_pipe.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/zeta_rom.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/butterfly_unit.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/butterfly_unit_pipe.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/ntt_core.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/basecase_mul.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/basecase_mul_pipe.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_zeta_rom.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_sync.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/sd_bram.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/common/pipeline_reg.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/comp_decomp/comp_decomp_sync.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v synth_design -top mlkem_top -part ${PART} -flatten_hierarchy rebuilt create_clock -name sysclk -period 20.000 [get_ports clk] report_timing_summary -file ${REPORT_DIR}/timing_synth.rpt report_timing -max_paths 10 -sort_by group -file ${REPORT_DIR}/timing_synth_worst.rpt report_utilization -file ${REPORT_DIR}/util_synth.rpt write_checkpoint -force ${REPORT_DIR}/mlkem_top_synth.dcp opt_design place_design route_design report_timing_summary -file ${REPORT_DIR}/timing_impl.rpt report_timing -max_paths 10 -sort_by group -file ${REPORT_DIR}/timing_impl_worst.rpt report_utilization -file ${REPORT_DIR}/util_impl.rpt write_checkpoint -force ${REPORT_DIR}/mlkem_top_impl.dcp