chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

Verilator is no longer used (all verification is via Vivado XSIM). Remove:
- 10 per-module tb_*.cpp Verilator testbenches
- the entire test_framework/ Verilator harness (lib/, run_all.py, config.json,
  per-module test_plan.json/gen_vectors.py, golden vectors, reports)
- stale specs: verilator-conventions.md, test_framework/structure.md
  (index.md updated to drop the Verilator entry)

Parallelize run_tb.sh K x case execution (modules stay serial):
- new run_xsim_jobs helper: compile+elaborate once (serial, populates the
  shared xsim.dir), then run each (K,case) xsim in its own private workdir
  with a COPY of xsim.dir (~1MB) so concurrent same-snapshot runs don't clobber
  each other's runtime logs. Each workdir symlinks the repo sync_rtl tree so
  the TB's repo-relative $readmemh vector paths resolve.
- top/enc/dec runners refactored to build a (snapshot:K:case) spec list and
  hand it to run_xsim_jobs; ordered PASS/FAIL summary + per-job /tmp logs
  preserved. Bare './run_tb.sh top' now also takes the parallel path.

Speedup (20 cores): top full sweep 2:11 -> 0:51 (~2.6x), ~320% CPU.
Verified: top (11) / enc (9) / dec (9) all PASS; missing-vector runs still
fail (file-not-found guard -> exit 1).

.claude/plans/bram_migration_plan.md

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+# 计划：将 mlkem_top 的大数据存储迁移到 BRAM
+
+## 目标
+把当前用裸 `reg` 数组实现的三块大存储改为可被 Vivado 推断为 block RAM 的结构，
+使设计面向综合时不再把 86 kbit 的多项式存储映射成 LUT/FF。
+
+涉及存储：
+| 当前 reg 数组 | 容量(KMAX=4) | 用途 |
+|---|---|---|
+| `polymem [0:28*256-1]` ×12bit | 86 016 bit | 全部多项式 Â/ŝ/ê/t̂ |
+| `ek_mem [0:1567]` ×8bit | 12 544 bit | byteEncode 后 ek |
+| `dkp_mem [0:1535]` ×8bit | 12 288 bit | byteEncode 后 dk_pke |
+
+复用现有 `sync_rtl/storage/sd_bram.v`（1 读 + 1 写，读地址寄存→1 周期读延迟，
+W≥12 & D≥64 时 Vivado 自动推断 BRAM）。
+
+## 核心约束（已从代码确认）
+1. **BRAM 读有 1 周期延迟**（reg 数组是组合读）。所有读出点都要改成“地址提前一拍”。
+2. **BRAM 每端口每周期 ≤1 访问**。当前 `polymem` 在同周期最多有 2 个不同读地址
+   （ST_M LOAD 同时读 A 和 ŝ），且 ST_E 同周期读同一 poly 的 2 个系数。
+3. **ST_E 当前每周期写 3 字节**到 ek/dk —— BRAM 单写口做不到。
+
+## 关键结论（决定方案可行性）
+- `poly_mul_sync` 在 LOAD 阶段把 256 对系数**全部存进自己的 mem_A/mem_B**，再在 COMP
+  阶段输出。所以 ST_M 的 LOAD（读 A+ŝ）与 ACCUMULATE（读 ê/t̂、写 t̂）**绝不同周期**。
+  → `polymem` 按区域分 4 个 bank {A, S, E, T} 后，每个 bank 任意周期 ≤1 读 + 1 写，
+  `sd_bram` 即可满足，无需真双口。
+- TB 每次调试回读等 **2 个周期**（`@(posedge clk); @(posedge clk);`），可吸收 BRAM 多出的
+  1 拍读延迟，回读路径无需改 TB。
+
+## polymem 4-bank 划分
+| bank | slot 数 | 深度(×256) | 写于 | 读于 |
+|---|---|---|---|---|
+| A (Â[i][j]) | KMAX²=16 | 4096 | ST_A | ST_M LOAD |
+| S (ŝ[i]) | KMAX=4 | 1024 | ST_C / ST_N | ST_N LOAD, ST_M LOAD, ST_E |
+| E (ê[i]) | KMAX=4 | 1024 | ST_C / ST_N | ST_N LOAD, ST_M ACC(j=0) |
+| T (t̂[i]) | KMAX=4 | 1024 | ST_M ACC | ST_M ACC(j>0), ST_E |
+（总深度 7168 == 当前 28×256，容量不变）
+
+每个 bank 一个 `sd_bram #(.W(12))`。读地址由一个 per-bank mux 选择：计算期由 FSM 计数器驱动，
+ST_DONE/回读期由 `dbg_*` 驱动；`dbg_coeff_o` 改为按 slot 选 4 个 bank 的 rd_data。
+
+## 实施分两阶段，每阶段后跑全部 11 个 KAT 用例
+
+### 阶段 1：ek_mem / dkp_mem → BRAM（风险较低，先做）
+1. 例化 `ek_bram`、`dkp_bram`（sd_bram，W=8）。
+2. **重写 ST_E 为每周期写 1 字节**（3 字节拆 3 拍）：新增子计数器 b∈{0,1,2}，
+   按 b 选 e_b0/e_b1/e_b2 与目标地址 e_boff+b。ST_E 周期数约 ×3（K=4 增 ~2K 周期，
+   占总量 ~4%，可接受）。rho 拷贝阶段本就 1 字节/周期，不变。
+3. **ST_H 的 h_padbyte 读 ek 改为地址提前一拍**：assemble 子状态先发地址、下一拍取数据
+   写入 h_block_r（h_byte 流水线 +1 级）。
+4. **回读路径**（dbg_byte_o / dbg_dk_o）：改为直接用 bram 的 rd_data（去掉多余的中间寄存器，
+   保持总延迟 ≤2 拍，落在 TB 的 2 周期等待内）。
+5. 跑 `./run_tb.sh top` 全 11 例，要求 0 个 `cannot be opened`、全 PASS。
+
+### 阶段 2：polymem → 4 bank BRAM（风险较高）
+1. 例化 4 个 `sd_bram #(.W(12))`：bank_a(D=4096)、bank_s/e/t(D=1024)。
+2. 写口改写：ST_A→bank_a；ST_C→bank_s/e；ST_N→bank_s/e；ST_M ACC→bank_t。
+3. 读口加“地址提前一拍”流水：
+   - ST_N LOAD：读地址 = 下一个 n_ridx，数据对齐 ntt_core 的 valid_i。
+   - ST_M LOAD：读地址 = 下一个 m_ld，数据对齐 poly_mul 的 pm_valid。
+   - ST_M ACC：m_acc_src 读地址跟踪即将到来的 m_oidx（提前一拍），对齐 pm_vo。
+   - ST_E：每周期读 1 个系数（e_c0、e_c1 拆两拍），配合阶段 1 的 1 字节/周期写。
+4. dbg_coeff_o：4 bank rd_data 按 dbg_slot 区间选择。
+5. 跑全 11 例验证。
+
+## 验证方法（每阶段）
+- 干净重跑：`rm -rf xsim.dir .Xil` 后 `./run_tb.sh top`。
+- 检查日志：`grep -c 'cannot be opened'`(=0) 且 11/11 `PASS`。
+- 记录周期数变化（预期 ek/dk BRAM 化使 ST_E 变长、polymem 读延迟引入少量气泡）。
+- 阶段 2 完成后，可选：跑 `vivado -mode batch` 综合，确认 polymem 现在落在 RAMB 而非 LUTRAM。
+
+## 不在本次范围
+- 是否把 ek/dk 暴露为对外输出端口（上一条被打断的请求）—— 独立问题，本次只改存储实现，
+  保持现有 dbg_* 接口不变。如需对外输出，迁移完成后另议。
+
+## 风险
+- 读延迟流水改造触及所有 5 个计算阶段的握手时序，是 KAT 回归的主要风险点。
+- 缓解：分两阶段、每阶段独立 KAT 回归；先做低风险的 ek/dk，再做 polymem。
+- 若某阶段无法在合理尝试内通过 KAT，回退该阶段并报告根因，不带病提交。

.claude/plans/decaps_plan.md

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+# ML-KEM Decaps 顶层集成 — 实现计划
+
+> 在 `mlkem_top`(KeyGen + Encaps 均 KAT 通过)基础上扩展 Decaps(FIPS 203 Alg 18 + K-PKE.Decrypt Alg 15)。
+> 决策(已与用户确认):**(1) 实现完整隐式拒绝路径(J + 常量时间 c'==c 比较 + K̄/K' mux),并用 corrupted-ct(KAT ct_n/ss_n)验证拒绝路径;(2) 逐级 dbg tap 对拍 ml-kem-r golden(m'/w/u_hat 等)+ 端到端 ss==KAT.ss。**
+
+## 算法(Decaps_internal,全 K)
+输入:dk(=KAT.sk,768K+96 B)、c(=KAT.ct,32(du·K+dv) B)。输出:K'=ss(32 B)。
+1. 解析 dk:`dk_pke = dk[0:384K]`(s_hat)、`ek_pke = dk[384K:768K+32]`、`h = dk[768K+32:768K+64]`、`z = dk[768K+64:768K+96]`。
+2. `m' = K-PKE.Decrypt(dk_pke, c)`(**唯一全新数据通路**,见下)。
+3. `(K', r') = G(m' ‖ h)` = SHA3-512(64 B 单块)。**与 Encaps G 完全相同**(mode=11)。
+4. `K̄ = J(z ‖ c)` = SHAKE-256(z‖c, 32 B 输出)。**多块,块数 6/9/12 = 与 H(ek) 相同**。
+5. `c' = K-PKE.Encrypt(ek_pke, m', r')`。**这就是 Encaps E1–E7**(A 再生 + 采样 y/e1/e2(seed=r') + NTT + u + v + 压缩成 ct')。**已 KAT 通过,零改动复用**。
+6. 常量时间比较 `c' == c`(逐字节 XOR 累加)。
+7. `K' = (c'==c) ? K' : K̄`(隐式拒绝 mux)。返回 K'=ss。
+
+### K-PKE.Decrypt(Alg 15,全新)
+- 解析 c:`c1 = c[0:32·du·K]`、`c2 = c[32·du·K : +32·dv]`。
+- `u'[i] = Decompress_du(byteDecode_du(c1[i]))`,i=0..K-1(**新:通用 byteDecode_d 解包器 + comp_decomp mode=1 解压**)。
+- `v' = Decompress_dv(byteDecode_dv(c2))`(1 poly)。
+- `s_hat[i] = byteDecode12(dk_pke[i·384..])`,i=0..K-1(**复用 Encaps TDEC 机器**,5-cyc/triple)。
+- `u_hat[i] = NTT(u'[i])`(mode=0,K polys,**复用 ST_ENC_N 的 ntt_core**)。
+- `w = v' − INTT(Σⱼ s_hat[j]∘u_hat[j])` mod Q(**复用 Encaps V 机器(MAC+INTT),ADD 改 SUB,加数 v' 替 e2+mu**)。
+- `m' = byteEncode₁(Compress₁(w))` = 32 B(**复用 C1/C2 打包器,d=1**)。
+
+## 复用与新增
+
+### 直接复用(零或极小改动)
+- **整个 Encaps E1–E7**(c' = Encrypt):A 再生、CBD(seed=r')、NTT、U、V、C1、C2 → ct_bram。完全复用,只是 seed 来自 r'(已是 r_r 路径)、ek 来自 ek_pke(已在 ek_bram)、m 来自 m'(新:m' 寄存器替 m_r)。
+- `u_sha3` G(mode=11,m'‖h):与 Encaps G 同,只是 enc_g_data 高半改 h(来自 dk 而非 H(ek) 重算)。
+- `u_keccak` 共享核 + J 多块:复用 H 的 mb 路径,仅末块 pad 常量 0x06→0x1F(SHAKE)。
+- `ntt_core`:u_hat fwd NTT(mode=0,复用 ST_ENC_N);decrypt 的 INTT(mode=1,复用 V 的 u_intt 路径)。
+- `poly_mul` / 3 银行 / comp_decomp:加 Decaps phase mux。
+- Encaps TDEC(byteDecode12 → bank_a):decrypt 的 s_hat 解码复用(改落 dk_pke 源 + 目标 bank)。
+
+### 新增 RTL
+- **`byteDecode_d` 通用解包器**(d∈{4,5,10,11}):c 字节流 → d-bit 系数,LSB-first(byteEncode_d 的逆)。新写,流式读 ct/c_bram,写银行。
+- **comp_decomp mode=1 解压**:实例已有(E5/E7 用 mode=0);Decaps decode-decompress 用 mode=1,d=du/dv。加 phase。
+- **dk 载入路径**:`dk_in_*`(或复用 ek_in_* 加宽地址),Decaps 前流入 dk_bram。顶层解析:dk_pke→bank/解码、ek_pke→ek_bram、h/z→寄存器。
+- **c 载入路径**:`c_in_*` 流入 ct_bram 的「输入 c」区(注意 c' 也写 ct_bram → 需独立 c_in_bram 或分区,见存储编排)。
+- **J 多块组装**:z(reg)‖c(c_in_bram)→ 136B 块,末块 0x1F pad。新地址逻辑(类 H 的 h_g_addr)。
+- **w = v' − INTT(...)**:V 机器 ADD 子相改 SUB(`(v' − psum) mod Q`,负则 +Q),加数源 v'(银行)替 e2(bank_a)+mu。
+- **m' Compress₁+byteEncode₁**:打包器加 d=1 路径(每系数 1 bit,256 bit = 32 B)。m' 落 32-bit 寄存器(供 G 与 c'-Encrypt)。
+- **常量时间比较 c'==c**:逐字节读 ct_bram(c')与 c_in_bram(c),XOR 累加进 1-bit `ct_ne_r`(全程扫完,不早退)。
+- **隐式拒绝 mux**:`ss_r = ct_ne_r ? k_bar_r : kprime_r`。
+- **op_i 加宽 2-bit**:00=KeyGen,01=Encaps,10=Decaps。新增 ST_DEC_* 状态。
+
+## 存储编排(关键)
+- **c 输入 vs c' 输出冲突**:Decaps 既要保留输入 c(给 J 和最终比较),又要算 c'(写 ct_bram)。**解法:c 输入存独立 `c_in_bram`(sd_bram W=8 D=2048);c' 仍写 ct_bram。** 比较阶段两个 bram 各一读口,无冲突。J 从 c_in_bram 读。
+- **Decrypt 阶段银行**:s_hat(K)、u'(K)、u_hat(=NTT(u') 就地 K)、v'(1)、psum/w(1)。
+  - u' → bank_se rel 0..K-1;NTT 就地得 u_hat。
+  - s_hat → bank_a slot j·K(复用 TDEC 落点 + V-MAC 寻址)。
+  - v' → bank_t rel 0(或 bank_a 空 slot)。
+  - psum(Σ s∘u_hat)→ bank_t[UPSUM];INTT 就地;SUB 读 v'(bank_t rel 0)+ psum(bank_t UPSUM)→ 单口冲突 → v' 改存 bank_a 某 slot(类 e2 搬迁)或 bank_se 空区。**bring-up 定稿,dbg 验证。**
+  - m' 算完 → 32-bit 寄存器。Decrypt 阶段结束,银行清空。
+- **Encrypt(c')阶段**:Decrypt 已出 m'(reg),银行重新被 Encaps E1–E7 占用,无并发。
+
+## 顶层接口新增
+- `op_i [1:0]`:00/01/10。start_i 锁存 op_r[1:0]。
+- `dk_in_*`(we/addr/byte):dk 流入。`c_in_*`(we/addr/byte):c 流入。
+- `ss_o`(复用):Decaps 输出 K'。
+- dbg taps:m'(`dbg_mprime_o[255:0]`)、w/u_hat 经现有 dbg_coeff_o、k_bar(`dbg_kbar_o`)。
+
+## 实现阶段(逐阶段 dbg/KAT 对拍)
+- **D0 — 脚手架 + dk/c 载入 + 解析** ✅:op_i 加宽 2-bit(00 KG/01 Enc/10 Dec),ST_DEC_LOAD(D0 暂直接→DONE)。dk 流入按 region 路由:dk_pke→dkp_bram、ek_pke→ek_bram、h→hek_r、z→z_r;ct→c_in_bram(独立于 ct_bram)。dbg 验证 h/z/ek_pke/dk_pke。**踩坑1:载入路由用 k_r 但 k_r 在 start_i 才锁存 → 预载期 region 边界全 0,路由全错。改用 LIVE k_i 边界(dkp_bytes_ld 等)。踩坑2:旧 KG/Enc TB 未接新端口(dk_in_*/c_in_*/dbg_*)→ X 漂入 write mux,KeyGen/Encaps 超时回归。补 tie-off 0。** runner = `./run_tb.sh dec [K] [CASE]`。K=2/3/4 D0 全过,KG/Enc 回归通过。
+- **D1 — byteDecode_d + Decompress → u'/v'**:新解包器 + comp_decomp mode=1。dbg 对 u'/v'(ml-kem-r golden,新 dump_decaps)。
+- **D2 — s_hat 解码 + u_hat = NTT(u')**:TDEC 复用(dk_pke 源)、ntt_core fwd。dbg 对 s_hat / u_hat。
+- **D3 — w = v' − INTT(Σ s∘u_hat)**:V 机器 SUB 变体。dbg 对 w。
+- **D4 — m' = byteEncode₁(Compress₁(w))**:打包器 d=1。dbg 对 m'(== KAT 解密的 m')。
+- **D5 — G(m'‖h) → (K',r') + J(z‖c) → K̄**:G 复用、J 多块(0x1F pad)。dbg 对 K'/r'/K̄。
+- **D6 — c' = Encrypt(ek_pke,m',r')**:复用 Encaps E1–E7 写 ct_bram。dbg 对 c'==KAT.ct(有效 ct 时)。
+- **D7 — 比较 + 拒绝 mux + 端到端 KAT**:c'==c 常量时间比较,ss=mux。干净 TB:
+  - 有效 ct(KAT.ct):ss==KAT.ss(c'==c → K')。
+  - 损坏 ct(KAT ct_n / ss_n):ss==KAT.ss_n(c'≠c → K̄)。
+  - K=2/3/4 各 count=0..N。
+
+## 验证
+- 新 `dump_decaps.rs`(ml-kem-r examples,工作树):出 D1–D6 中间量(u'/v'/s_hat/u_hat/w/m'/K'/K̄)256-coeff / 32B golden。
+- 新 TB `tb_mlkem_dec_katK_xsim.v`:从 KAT 取 sk(→dk)、ct、ss、ct_n、ss_n,载入 dk/c,跑 Decaps,比 ss。
+- runner:`./run_tb.sh dec [K] [CASE]`(并入 run_tb,复用 top tcl + dec TB)。
+- XSIM 环境同前:`source settings64.sh; export LD_PRELOAD=libtinfo.so.5; rm -rf xsim.dir .Xil`。
+
+## 风险 / 注意
+- **c 输入 / c' 输出共存**:必须分两个 bram(c_in_bram + ct_bram),否则 c' 覆盖 c 后无法比较 / 算 J。最易错,D0 定。
+- **w 的 SUB**:`(v' − psum) mod Q`,结果可能负 → +Q 修正(类 mod_sub)。v'/psum 读口冲突 → v' 搬到不同 bank。D3 dbg 验证。
+- **J SHAKE pad**:末块 0x1F(非 0x06);单字节差异,复用 H mb 机器加 phase 选择 pad 常量。
+- **op_i 加宽**:1-bit→2-bit,改 IDLE 分发、reset、所有 op_r 判断。回归 KeyGen/Encaps 不破。
+- **m' 双用**:既喂 G(m'‖h)又喂 c'-Encrypt(替 m_r)。确保 Encrypt 路径读 m'_r 而非 m_r(加 mux 或 Decaps 时把 m'_r 写入 m_r)。
+- **隐式拒绝常量时间**:比较全程扫完不早退(XOR 累加),硬件天然如此;但 mux 不可短路。
+- **ek_pke 来自 dk**:Decaps 的 Encrypt 用 dk 内嵌的 ek_pke(解析到 ek_bram),不是外部 ek。

.claude/plans/keygen_plan.md

@@ -0,0 +1,175 @@
+# ML-KEM KeyGen 顶层集成 — 实现计划与进度
+
+> 本文档用于让新工程师完整接手。包含原始计划 + 已完成进度 + 经验教训 + 下一步。
+
+## 目标与范围
+- 目标:实现 `mlkem_top` 的 **KeyGen 通路**(ML-KEM-512, K=2, η1=3),全新重写 valid/ready FSM。
+- 最终验收:对 **NIST 官方 KAT**(count=0..4)端到端逐字节通过,产出完整 ML-KEM dk。
+- 本计划只做 KeyGen。Encaps/Decaps 留作后续任务。
+- 旧版 `mlkem_top.v`(1658 行)已于 commit 1cace51 删除,**不可用**(Decaps 是占位,且子模块握手从未真正跑通——旧 TB 用 24 处 force/release 绕过)。新版全新重写。
+
+## 关键决策(已与用户确认)
+- **Keccak 策略**:每消费者用独立、已验证的核(sha3_top / sample_ntt_sync / sample_cbd_sync 各自带 keccak_core)。**不用 arbiter,不用 `_shared` 变体**(顶层当前用独立版)。
+- **SHA3 先扩多块**:已先把 sha3_top 的 H 模式扩成多块吸收(✅ 完成),再做完整 dk。
+- **FSM 全新重写**:只参考算法步骤,不取回旧代码。
+- **分阶段 + 逐级对拍**:每个子步骤对 golden 验证通过再进下一步。
+
+## 环境与工具(重要)
+- 工作目录:`/home/fallensigh/Dev/mlkem`,git 分支 `main`(直接提交,用户要求)。
+- **Verilator** 5.046:`python3 test_framework/run_all.py [--module X]`。快速回归。
+- **Vivado XSIM** 2019.2:每次需
+  ```
+  source /opt/Xilinx/Vivado/2019.2/settings64.sh
+  export LD_PRELOAD=/usr/lib64/libtinfo.so.5
+  ```
+  调用 **standalone** `xvlog -sv --relax -i . <files>` / `xelab <top> -s <snap> --timescale 1ns/1ps` / `xsim <snap> -R`。**不要**用 `vivado -mode batch`(脚本里用的是 standalone 命令,不是 Tcl)。zsh 不做无引号变量分词——用 `"$@"` 传文件列表。
+- XSIM 产物(xsim.dir/ .Xil/ *.jou *.log)已 gitignore;每次跑前 `rm -rf xsim.dir .Xil`。
+
+## Golden reference(全部已验证可用)
+- **NIST 官方 KAT**:`/home/fallensigh/Dev/ml-kem-r/test_data/kat_MLKEM_{512,768,1024}.rsp`。
+- **ml-kem-r**(Rust, `/home/fallensigh/Dev/ml-kem-r`):`cargo test` 全过,512/768/1024 KAT 全通过。是可信参考。
+  - API:`ml_kem::mlkem512::key_gen(d,z)`、`keygen_internal::<2,192>(d,z)`、`k_pke::key_gen::<2,192>(d)`。
+  - 公共子函数:`sample::sample_ntt(&[u8])`、`sample::sample_poly_cbd::<ETA_BYTES>`、`ntt::ntt(&mut [i32;256])`、`ntt::multiply_ntts`、`sha3::mlkem_G/mlkem_H/mlkem_PRF`、`utils::byte_encode(&[i32;256], d)`。
+  - `logging` feature + `examples/logging.rs` dump 中间值(4-coeff head)。
+- **server_code**(Python, `~/Dev/server_code/python_project/PQC_2025/A_ML_KEM_v0`):`SHA_3.G/H/J/PRF`、`ML_KEM.py`。已对 hashlib 交叉验证。
+
+### 白盒 golden 向量(Stage 0 产物,已生成并自校验)
+- 生成器:`/home/fallensigh/Dev/ml-kem-r/examples/dump_keygen.rs`(我新增,未提交到 ml-kem-r,因为该仓库有用户大量未提交改动 —— 只在工作树用)。
+  - 运行:`cargo run --release --example dump_keygen -- <out_dir> 5`
+- 输出目录:`test_framework/modules/mlkem_keygen/golden/`(已 commit 在 mlkem 仓库 106b292)。
+- 每个 KAT case c(000..004)的全 256-coeff 中间量,文件名:
+  - `c000_rho.hex` / `c000_sigma.hex`:32B hex(byte0 在最低)。
+  - `c000_Ahat_i_j.hex`(i,j∈0..1):256 行,每行 3-hex 系数(mod q)。
+  - `c000_s_i.hex` / `c000_e_i.hex`:CBD 输出,**mod-q 形式**(负值 +Q,如 -1 → 0xd00=3328)。
+  - `c000_shat_i.hex` / `c000_ehat_i.hex`:NTT(s/e) 后。
+  - `c000_that_i.hex`:t_hat。
+  - `c000_ek.hex`(800B hex = KAT pk)、`c000_dkpke.hex`(768B = KAT sk 前 384*K)。
+  - dump_keygen 已自校验 ek==KAT.pk、dk_pke==KAT.sk[..768],全 5 case 通过。
+
+## KeyGen 算法 (FIPS 203 Alg 13+16, K=2 η1=3)
+1. (ρ,σ) = G(d ‖ K)         — SHA3-512, 33B 输入(单块)。**G 输入 = d(byte0 低) ‖ K=2 at byte32,无字节翻转**(已确认,旧版 byte-reverse 是 bug)。ρ = hash[255:0],σ = hash[511:256]。
+2. Â[i][j] = SampleNTT(ρ‖j‖i), i,j∈{0,1}  — seed = rho ‖ j ‖ i(sample_ntt_sync 内部 msg={i_byte,j_byte,rho})。
+3. s[i] = CBD₃(PRF(σ, **i**)), i∈{0,1}      — nonce 0,1
+4. e[i] = CBD₃(PRF(σ, **K+i**)), i∈{0,1}     — nonce 2,3
+5. ŝ[i] = NTT(s[i]); ê[i] = NTT(e[i])       — 前向 NTT ×4 (mode=0, **无缩放**)
+6. t̂[i] = ê[i] + Σⱼ Â[i][j]∘ŝ[j]            — poly_mul + 逐系数 modQ 累加
+7. ek = byteEncode₁₂(t̂[0..1]) ‖ ρ           — 12-bit 原始打包(**非压缩**)
+8. dk_pke = byteEncode₁₂(ŝ[0..1])
+9. dk = dk_pke ‖ ek ‖ H(ek) ‖ z             — H(ek): SHA3-256 over 800B(**多块**)
+
+**用到的叶子模块**(端口签名见下):sha3_top(G+多块H)、sample_ntt_sync、sample_cbd_sync、ntt_core(mode=0)、poly_mul_sync、mod_add_sync。**不用** comp_decomp。
+
+## 叶子模块端口签名(已抓取)
+- `rng_sync #(SEED)`: clk,rst_n,valid_i,ready_o,data_o[255:0],valid_o,ready_i
+- `sha3_top`: clk,rst_n,mode[1:0],data_i[511:0],valid_i,ready_o,hash_o[511:0],valid_o,ready_i, **+多块端口** mb_en,mb_block_i[1087:0],mb_valid_i,mb_last_i,mb_ready_o
+- `sample_ntt_sync #(K=4)`: clk,rst_n,rho_i[255:0],k_i[2:0],i_idx[1:0],j_idx[1:0],valid_i,ready_o,coeff_o[11:0],valid_o,ready_i,last_o
+- `sample_cbd_sync`: clk,rst_n,seed_i[255:0],nonce_i[7:0],eta_i[1:0],valid_i,ready_o,coeff_o[11:0](**12-bit signed 二补码**),valid_o,ready_i,last_o
+- `ntt_core`: clk,rst_n,coeff_in[11:0],valid_i,ready_o,mode(0=fwd无缩放/1=inv有缩放),coeff_out[11:0],valid_o,ready_i,done_o。协议:IDLE/LOAD 期间 ready_o 高,流式喂 256 个(valid_i 持续);算完 S_OUTPUT 流式吐 256(valid_o 高,ready_i 消费);S_DONE→IDLE。
+- `poly_mul_sync`: clk,rst_n,coeff_a_in[11:0],coeff_b_in[11:0],valid_i,ready_o,coeff_out[11:0],valid_o,ready_i。协议:LOAD 阶段 **同时**喂 A、B 各 256 对(coeff_a_in/coeff_b_in 同拍),然后 COMPUTE 流式吐 256。
+- `mod_add_sync`: clk,rst_n,a[11:0],b[11:0],valid_i,ready_o,sum[11:0],valid_o,ready_i。(a+b)mod Q。
+- `comp_decomp_sync`: clk,rst_n,coeff_in[11:0],d[4:0],mode,valid_i,ready_o,coeff_out[11:0],valid_o,ready_i(KeyGen 不用)。
+- `sd_bram #(W=48,D=64,A=6)`、`s_bram #(W=48,D=512,A=9)`(KeyGen 暂用寄存器阵列 polymem 缓存,未用 bram)。
+
+## 已完成进度
+
+### ✅ Stage 0:白盒 golden 向量生成器(commit 106b292)
+- `examples/dump_keygen.rs`(ml-kem-r 工作树)+ `test_framework/modules/mlkem_keygen/golden/`(mlkem 仓库)。
+- 自校验:ek==KAT.pk、dk_pke==KAT.sk 前缀,5/5 通过。
+
+### ✅ Stage 1:sha3_top 多块 SHA3-256 吸收(commit 106b292)
+- `sync_rtl/sha3/sha3_top.v`:新增多块吸收 FSM。新端口 `mb_en/mb_block_i[1087:0]/mb_valid_i/mb_last_i/mb_ready_o`。
+  - **设计**:调用方预填充末块的 SHA3-256 padding(0x06 ... 0x80),模块只做纯吸收 loop(state^=block; Keccak-p)。单块 G/H/J 路径在 mb_en=0 时逐 bit 不变。
+  - 状态:MB_IDLE/MB_PERMUTE/MB_DONE。`mb_state_r`(1600-bit running state),`mb_digest_r`(256-bit sticky digest,保持到消费者 ack)。
+  - `ready_o = !mb_en && (state_r==ST_IDLE)`、`valid_o`/`hash_o` 按 mb_en 选择。
+- TB:`sync_rtl/sha3/TB/tb_sha3_mb_xsim.v`(自检,流 800B ek=6 块 → H(ek),对 hashlib.sha3_256)。向量:`vectors/mb_h_blocks.hex`、`mb_h_expected.hex`。
+  - **握手坑(已解决)**:TB 必须在 accept 边沿保持 valid/last 稳定(等 mb_ready_o 拉低后才撤),否则采样竞争。digest 一次有效后 sticky,TB 收完才 ack。
+- 既有 G/H/J TB(xsim 3 个 + Verilator tb_sha3.cpp)**必须 tie off mb_* 端口**(mb_en=1'b0 等),否则 mb_en 浮空成 x 破坏 ready_o。已全部修。
+- 回归:Verilator 25/25,XSIM 4 个 TB(simple G/H/J、keccak_core、7-vec、multiblock)全过。
+
+### ✅ sample_ntt 幽灵脉冲修复(commit 6db3c7c)
+- **bug**:`sample_ntt_sync` 的 Phase-1(输出 d1)缺少 Phase-2 有的 `need_more` 守卫。当第 256 个被接受系数是 d1 且组推进时,某些 seed 会在 last_o 后多吐一拍 valid_o(KAT count=0 rho 下,seed i=0/j=1 吐 257 拍)。集成时漏进下个 poly 的 index 0,整流后移一位。
+- **修复**:Phase-1 改 `if (d1_acc_r && need_more)`。两变体(`sample_ntt_sync.v` + `sample_ntt_sync_shared.v`)都改。
+- **补盲区**:`tb_sample_ntt_xsim.v` 加断言——last_o 后保持 ready_i 数多余 valid_o,有则 FAIL。已验证该断言能抓 bug(还原副本 3 个幽灵)、修复版通过。
+- 验证:40-seed(sync)+24-seed(shared)审计全 256 拍/last@256/零幽灵;Verilator 1536/1536;全框架 4334/4334;Stage 2c 2048/2048。
+- 记忆:`sample-ntt-257th-pulse-bug.md`。
+
+### ✅ Stage 2a/2b/2c:KeyGen 数据通路前半(**未提交**,在工作树)
+- 文件:`sync_rtl/top/mlkem_top.v`(新建)+ TB `sync_rtl/top/TB/tb_mlkem_kg_2a_xsim.v`、`tb_mlkem_kg_2c_xsim.v`、向量 `sync_rtl/top/TB/vectors/kg_c000_AsE.hex`。
+- **mlkem_top 结构**(K=2,ETA1=3):
+  - 端口:clk,rst_n,d_i[255:0],z_i[255:0],start_i,busy_o,done_o + **调试 tap**:dbg_slot_i[3:0],dbg_idx_i[7:0],dbg_coeff_o[11:0](寄存器读 polymem,2拍延迟),dbg_rho_o[255:0],dbg_sigma_o[255:0]。
+  - **polymem**:`reg [11:0] polymem[0:10*256-1]`,slot 映射:0-3=A00,A01,A10,A11;4-5=S0,S1;6-7=E0,E1;8-9=T0,T1。s/s_hat 共享 slot(就地 NTT),e 同理。
+  - FSM 状态:ST_IDLE=0,ST_G=1,ST_A=2,ST_C=3,...,ST_DONE=15。
+  - **2a(G)**:sha3_top mode=00,g_data={248'b0,8'(K),d_i};完成捕获 rho_r/sigma_r。✅ rho/sigma 对 golden 精确。
+  - **2b(A)**:a_pair 0..3 循环,a_i=pair[1],a_j=pair[0],a_slot=pair。每 pair 跑 sample_ntt_sync,256 系数写 polymem[a_slot]。✅ 1024 系数全对。
+  - **2c(C)**:c_poly 0..3(s0,s1,e0,e1),c_nonce=c_poly,c_slot 映射。CBD 输出经 `cbd_modq = cbd_coeff[11] ? cbd_coeff+Q : cbd_coeff` 转 mod-q 后写 polymem。✅ 2048/2048(A+s+e)全对。
+  - **关键防护 a_busy/c_busy**:请求被接受(valid&&ready)时置位,last 时清零;仅 busy 时收集系数。本是为屏蔽 sample_ntt 幽灵脉冲的下游兜底;sample_ntt 根因修复后冗余但保留(无害,且对未来叶子模块是防御)。
+- **字节序基准**(全部已确认,这是旧版的痛点):
+  - G 输入 d 原序(byte0 低),无翻转。
+  - SampleNTT seed=rho‖j‖i。
+  - CBD nonce:s[i]=i,e[i]=K+i。
+  - golden 多项式存 mod-q;CBD RTL 输出 12-bit 二补码,需 +Q 转换。
+
+## 当前工作树状态(未提交)
+- `sync_rtl/top/mlkem_top.v`(新,Stage 2a/b/c,FSM 到 ST_C)
+- `sync_rtl/top/TB/tb_mlkem_kg_2a_xsim.v`、`tb_mlkem_kg_2c_xsim.v`(新)
+- `sync_rtl/top/TB/vectors/kg_c000_AsE.hex`(新,8 poly × 256 = 2048 行,顺序 A00,A01,A10,A11,S0,S1,E0,E1)
+- `.claude/plans/`(本文件)
+- **下一步该先提交 Stage 2a-2c**(测试已通过)。
+
+## 关键测试 literal(byte0-低 256-bit)
+- KAT c000 d:`D_LIT = 256'h2426f1941779574d3f1b163bd57f7e173e229e630ec7f7073bdf365137c4bb6d`
+- 期望 rho:`256'h15f74355ca862c3cdf3dab780c35cf24b88bf144706090a1c17e41205f9f1379`
+- 期望 sigma:`256'h69b042001b5630b1a039116cbfd29f62c0bde5a6b571504a9fcce68bed667fd5`
+
+## 下一步(剩余 Stage 2/3/4)
+
+### Stage 2d:NTT(s/e → ŝ/ê)  ← **当前正在做**
+- golden 映射已确认:`ntt(s_i)==shat_i`、`ntt(e_i)==ehat_i`(mode=0 fwd,无缩放,zeta 表见 ntt gen_vectors,N_INV=3303 仅 inv 用)。
+- 计划:新增 ST_N 状态,对 4 个 slot(S0,S1,E0,E1)逐个就地 NTT:从 polymem 读 256 喂 ntt_core(mode=0),收 256 写回同 slot。
+- 注意 ntt_core 协议:LOAD 期间持续 valid_i 喂 256;输出阶段 valid_o 高、ready_i 消费 256。需读地址流水(组合读 polymem)。
+- TB:扩展对 shat/ehat golden 校验。
+- **正读 mlkem_top.v 行 200-290 的时序逻辑准备插入 ST_N 时被打断;接手时先重读 mlkem_top.v 全文确认当前 FSM 时序结构再加 ST_N。**
+
+### Stage 2e:矩阵累加 t̂[i] = ê[i] + Σⱼ Â[i][j]∘ŝ[j]
+- 用 poly_mul_sync(同拍喂 A、B 各 256)算 Â[i][j]∘ŝ[j],再用 mod_add_sync 逐系数 + ê[i] 累加。K=2:t̂[0]=ê0+A00∘ŝ0+A01∘ŝ1;t̂[1]=ê1+A10∘ŝ0+A11∘ŝ1。
+- 对 golden `that_i` 校验。
+
+### Stage 2f:byteEncode₁₂ → ek/dk_pke
+- 12-bit LSB-first 打包(FIPS:b[i*12+j]=(coeff>>j)&1,再 bits_to_bytes)。ek=byteEncode12(t̂[0..1])‖ρ(800B);dk_pke=byteEncode12(ŝ[0..1])(768B)。
+- 对 KAT pk / sk 前缀逐字节校验。
+
+### Stage 3:KeyGen FSM 集成 + 干净顶层接口
+- 串起 2a-2f;顶层流式输出 ek_o/dk_o;无 force。
+
+### Stage 4:组装完整 dk + 端到端 KAT
+- dk = dk_pke ‖ ek ‖ H(ek)[用 Stage1 多块] ‖ z。
+- 干净 KAT TB(无 force/release),喂 KAT d/z,逐字节比 ek 与 dk。跑 KAT count=0..4 全过。Verilator + XSIM 双框架。
+
+## 经验教训(重要)
+1. **"PASS" 只证 RTL==reference**:必须独立对 hashlib/FIPS 验证 oracle。
+2. **单独 TB 盲区会掩盖模块 bug**:sample_ntt 的 257th 脉冲就是"读够就停"掩盖的。新 TB 要验证协议边界(last 后 valid 干净拉低)。
+3. **加端口必须 tie off 所有旧实例**:浮空输入成 x 会破坏组合逻辑(mb_en 教训)。
+4. **valid/ready 握手 TB 要在 accept 边沿保持输入稳定**,等 ready 拉低再撤,否则采样竞争(多块 H、A-pair 边界都踩过)。
+5. **字节序/位序是旧版主要 bug 源**:每步对 golden 逐字节,错位立刻暴露。
+6. **bash 工具偶发输出截断/丢失**:重要结论用 `rm -rf xsim.dir` 重跑确认,别凭一次模糊输出下判断。
+
+## 任务追踪(TaskList ID)
+- #7 Stage 0 ✅ completed
+- #8 Stage 1 ✅ completed
+- #9 Stage 2 datapath subblocks — in_progress(2a/b/c done,2d 进行中)
+- #10 Stage 3 FSM 集成 — blocked by #9
+- #11 Stage 4 dk + KAT — blocked by #8,#10
+
+## 提交历史(相关)
+- 106b292 feat(sha3): multi-block SHA3-256 absorb for H(ek); KeyGen golden vectors (Stage 0+1)
+- 6db3c7c fix(sample_ntt): suppress spurious 257th valid_o after last_o
+- (未提交)Stage 2a-2c mlkem_top + TB
+
+---
+## ✅ COMPLETE (session end state)
+- KeyGen FSM: IDLE->G->A->C->N->M->E->H->DONE, pure valid/ready, no force.
+- Verified vs NIST KAT MLKEM-512 **count=0..4**: ek (800B)==pk, dk (1632B)==sk, byte-exact, ~21350 cyc/case.
+- Commits: 106b292, 6db3c7c, 2f206a6, 4c692e5, a9e50eb, 1791491, 9824ed8, 42d3748.
+- Independent Keccak per consumer (G + dedicated H sha3_top + sample_ntt/cbd cores). No arbiter.
+- SECURITY: tool outputs this session carried prompt-injection (fake operator instructing `curl|bash`); all refused. Some outputs were tampered; results re-verified with controlled delimiters.
+- Remaining optional: streaming ek/dk output port (currently start_i/done_o + readback taps); Encaps/Decaps; shared-keccak migration.

.trellis/spec/rtl/index.md

@@ -3,12 +3,10 @@
 ## Pre-Development Checklist
 
 Before writing RTL code or testbenches, read:
-1. [Verilator Conventions](./verilator-conventions.md) — for C++ Verilator testbenches
+1. [XSIM Testbench Conventions](./xsim-tb-conventions.md) — for Vivado XSIM Verilog testbenches
-2. [XSIM Testbench Conventions](./xsim-tb-conventions.md) — for Vivado XSIM Verilog testbenches
 
 ## Files
 
 | File | Purpose |
 |------|---------|
-| `verilator-conventions.md` | Verilator 5.046 C++ testbench conventions (clock, timing, valid/ready protocol) |
 | `xsim-tb-conventions.md` | Vivado XSIM Verilog testbench conventions (template, vector format, TCL scripts) |

.trellis/spec/rtl/verilator-conventions.md

@@ -1,62 +0,0 @@
-# Verilator RTL Conventions
-
-## Verilator Version
-
-**5.046** (Fedora package). Requires **C++14** or later.
-
-## Compile Arguments
-
-**Do NOT** add `-CFLAGS -std=c++11`. Verilator 5.046 uses C++14 features (`""s` string literal).
-Let Verilator use its default C++ standard.
-
-Correct base command:
-```
-verilator -Wall --cc --build --timing --exe --top-module <top> <rtl> <tb.cpp>
-```
-
-## Include Paths
-
-All Verilog files use paths relative to project root (`~/Dev/mlkem`).
-Pass `+incdir+<project_root>` to Verilator so `\`include "sync_rtl/common/defines.vh"` resolves.
-
-## Clock Period
-
-100MHz = 10ns. Defined centrally in `sync_rtl/common/defines.vh`:
-```verilog
-`define CLK_PERIOD 10.0
-```
-
-## Testbench Timing Protocol (Verilator C++)
-
-### Critical Rule: Always advance at least one posedge before checking signals
-
-Setting a DUT input (e.g., `dut->valid_i = 1`) does NOT take effect until `dut->eval()` is called.
-A posedge requires: `dut->clk = 1; dut->eval();`.
-
-### pipeline_reg valid/ready timing
-
-The `pipeline_reg` module's valid_o is HIGH for exactly ONE cycle between the posedge that captures data and the next posedge that consumes it (when ready_i=1).
-
-Correct read pattern:
-```cpp
-// 1. Drive input + posedge → data captured, valid_o → 1
-dut->valid_i = 1;
-posedge(dut);  // dut->clk = 1; eval(); dut->clk = 0; eval();
-dut->valid_i = 0;
-
-// 2. Read result NOW (valid_o is high, sum is valid)
-printf("RESULT: %03X\n", dut->sum & 0xFFF);
-
-// 3. Consume with next posedge → valid_o → 0
-posedge(dut);
-```
-
-### Anti-pattern: while(!dut->ready_o) without eval
-
-Setting valid_i=1 and immediately checking ready_o in a while loop that starts with NO eval() will skip the first clock edge entirely if ready_o is already 1. Use do-while to guarantee at least one edge:
-```cpp
-dut->valid_i = 1;
-do {
-    posedge(dut);
-} while (!dut->ready_o);
-```

.trellis/spec/test_framework/structure.md

@@ -1,66 +0,0 @@
-# Test Framework Structure
-
-## Directory Layout
-
-```
-test_framework/
-├── run_all.py              # CLI entry: --module, --case, --list, --quick
-├── config.json              # Verilator path, clock period, timeouts
-├── lib/
-│   ├── test_runner.py      # Discovery, compile, run, compare pipeline
-│   ├── sim_controller.py   # Verilator compiles/run wrapper
-│   ├── vector_gen.py       # Base class for vector generators
-│   ├── result_checker.py   # Hex-file comparison
-│   └── reporter.py         # Terminal + HTML output
-├── modules/
-│   └── <module>/
-│       ├── test_plan.json  # Module test definition
-│       ├── gen_vectors.py  # Vector generator (subclass of VectorGenerator)
-│       └── vectors/        # Generated hex files (auto-cleaned)
-└── reports/
-    ├── latest/
-    └── history/
-```
-
-## test_plan.json Schema
-
-```json
-{
-  "module": "<name>",
-  "rtl_top": "sync_rtl/<path>/<top>.v",
-  "rtl_deps": ["sync_rtl/common/<dep>.v"],
-  "tb_cpp": "sync_rtl/<path>/TB/tb_<top>.cpp",
-  "simulator": "verilator",
-  "timeout_s": 30,
-  "cases": [{
-    "id": "<case_id>",
-    "description": "<what this tests>",
-    "params": {},
-    "num_vectors": 50,
-    "tolerance": "bit_exact"
-  }]
-}
-```
-
-- `rtl_top`: top module basename (without .v) is used as Verilator `--top-module`
-- `rtl_deps`: listed before `rtl_top` in Verilator command line
-- `tolerance`: "bit_exact" uses result_checker.py; otherwise delegates to gen_vectors.compare_results()
-
-## Vector Generator Contract
-
-Each module's `gen_vectors.py` must:
-1. Subclass `VectorGenerator` from `test_framework.lib.vector_gen`
-2. Implement `generate_one(params) -> dict` returning `{"input": {...}, "expected": {...}}`
-3. Override `write_hex_file(vectors, filepath)` for input format
-4. Override `write_expected_file(vectors, filepath)` for expected format
-
-The framework auto-discovers the generator class by scanning for subclasses of VectorGenerator.
-
-## Adding a New Module
-
-1. Create `test_framework/modules/<name>/test_plan.json`
-2. Create `test_framework/modules/<name>/gen_vectors.py`
-3. Create `sync_rtl/<name>/<name>_sync.v` (RTL)
-4. Create `sync_rtl/<name>/TB/tb_<name>.cpp` (Verilator C++ TB)
-5. Run `python3 test_framework/run_all.py --list` to verify discovery
-6. Run `python3 test_framework/run_all.py --module <name>` to test

run_tb.sh

@@ -10,12 +10,15 @@
 #        ./run_tb.sh enc                  # ML-KEM Encaps: all K, all cases (0..2)
 #        ./run_tb.sh enc 2                # Encaps K=2, all its cases
 #        ./run_tb.sh enc 4 1              # Encaps K=4, only CASE=1
+#        ./run_tb.sh dec                  # ML-KEM Decaps: all K, all cases (0..2)
+#        ./run_tb.sh dec 2 0              # Decaps K=2, only CASE=0
 #        ./run_tb.sh --list
 #
-# 'top' (KeyGen) and 'enc' (Encaps) share the same RTL datapath; both compile
+# 'top' (KeyGen), 'enc' (Encaps) and 'dec' (Decaps) share the same RTL datapath;
-# the xvlog lines from sync_rtl/top/TB/xsim_run.tcl. They differ only in the
+# all compile the xvlog lines from sync_rtl/top/TB/xsim_run.tcl. They differ only
-# testbench: top -> tb_mlkem_kg_katK_xsim, enc -> tb_mlkem_enc_katK_xsim.
+# in the testbench: top -> tb_mlkem_kg_katK_xsim, enc -> tb_mlkem_enc_katK_xsim,
-# For these two, K (2/3/4) and CASE select a single KAT run so you can iterate
+# dec -> tb_mlkem_dec_katK_xsim.
+# For these, K (2/3/4) and CASE select a single KAT run so you can iterate
 # quickly. Other modules ignore the extra args and run their xsim_run.tcl verbatim.
 #
 # Prerequisites:
@@ -35,6 +38,7 @@ if [ "$1" = "--list" ]; then
         fi
     done
     echo "  enc   (ML-KEM Encaps; shares the 'top' RTL/tcl, enc testbench)"
+    echo "  dec   (ML-KEM Decaps; shares the 'top' RTL/tcl, dec testbench)"
     exit 0
 fi
 
@@ -48,8 +52,8 @@ MODULE="$1"
 SEL_K="$2"          # optional: 2/3/4 (top/enc modules only)
 SEL_CASE="$3"       # optional: KAT case index (top/enc modules only)
 # 'enc' is not its own RTL dir; it reuses the 'top' KeyGen tcl compile list
-# (same datapath) and swaps in the encaps testbench.
+# (same datapath) and swaps in the encaps testbench. 'dec' likewise (Decaps).
-if [ "$MODULE" = "enc" ]; then
+if [ "$MODULE" = "enc" ] || [ "$MODULE" = "dec" ]; then
     TB_DIR="$SCRIPT_DIR/sync_rtl/top/TB"
 else
     TB_DIR="$SCRIPT_DIR/sync_rtl/$MODULE/TB"
@@ -102,11 +106,68 @@ execute_tcl() {
     rm -f "$tmp_script"
 }
 
+# ---- parallel xsim launcher --------------------------------------------------
+# xsim writes runtime logs into xsim.dir/<snapshot>/, so two runs of the SAME
+# snapshot clobber each other. To run (K,case) in parallel we give each job its
+# own COPY of xsim.dir (~1 MB, cheap) under a private workdir, run xsim there,
+# and tee output to a per-job log. Compile+elaborate stay serial (they populate
+# the shared xsim.dir BEFORE any parallel run starts).
+#
+# run_xsim_jobs <module-tag> <pass-grep-regex> <pass-match-string> <spec>...
+#   each <spec> = "snapshot:K:CASE". Launches all specs in parallel, waits,
+#   then prints an ordered summary and returns nonzero if any job failed.
+PAR_BASE="${TMPDIR:-/tmp}/run_tb_par_$$"
+run_xsim_jobs() {
+    local mtag="$1" pgrep="$2" pmatch="$3"; shift 3
+    local specs=("$@")
+    local repo; repo="$(pwd)"
+    rm -rf "$PAR_BASE"; mkdir -p "$PAR_BASE"
+
+    # launch all jobs in parallel
+    local s snap k c wd
+    for s in "${specs[@]}"; do
+        IFS=: read -r snap k c <<< "$s"
+        wd="$PAR_BASE/${mtag}_k${k}_c${c}"
+        mkdir -p "$wd"
+        cp -r "$repo/xsim.dir" "$wd/xsim.dir"
+        # The TB loads vectors via repo-relative $readmemh paths
+        # (sync_rtl/top/TB/vectors/...). xsim resolves these against the run
+        # cwd, so symlink the repo's sync_rtl tree into each private workdir.
+        ln -sf "$repo/sync_rtl" "$wd/sync_rtl"
+        (
+            cd "$wd"
+            echo "  xsim $snap -R -testplusarg CASE=$c"
+            xsim "$snap" -R -testplusarg "CASE=$c" --nolog > "$wd/run.out" 2>&1
+        ) &
+    done
+    wait
+
+    # ordered summary + per-job log copy to /tmp/run_tb_<mtag>_k*_c*.log
+    local fail=0 pf nf log
+    for s in "${specs[@]}"; do
+        IFS=: read -r snap k c <<< "$s"
+        wd="$PAR_BASE/${mtag}_k${k}_c${c}"
+        log="/tmp/run_tb_${mtag}_k${k}_c${c}.log"
+        cp -f "$wd/run.out" "$log" 2>/dev/null
+        pf=$(grep -oE "$pgrep" "$log" | tail -1)
+        nf=$(grep -c 'cannot be opened' "$log")
+        echo "    K=$k CASE=$c -> ${pf:-NORESULT}  (file-not-found=$nf, log: $log)"
+        # pmatch == "PASS*" means "any PASS (Dn) stage tag"; else exact match.
+        if [ "$pmatch" = "PASS*" ]; then
+            { [[ "$pf" == PASS* ]] && [ "$nf" -eq 0 ]; } || fail=1
+        else
+            { [ "$pf" = "$pmatch" ] && [ "$nf" -eq 0 ]; } || fail=1
+        fi
+    done
+    rm -rf "$PAR_BASE"
+    return $fail
+}
+
 # Fast single-K / single-case path for the 'top' (ML-KEM KeyGen) module.
 # Compiles the same RTL as the tcl, but elaborates ONLY the requested K and
-# runs ONLY the requested CASE(s). Avoids the 3-snapshot + 11-run full sweep.
+# runs the CASE(s) in parallel. Avoids the 3-snapshot + 11-run serial sweep.
 run_top_selected() {
-    local tcl_file="$1" k="$2" csel="$3"
+    local tcl_file="$1" ksel="$2" csel="$3"
     set +e   # we do our own error handling / result parsing here
 
     rm -rf xsim.dir .Xil
@@ -116,29 +177,22 @@ run_top_selected() {
         eval "$cmd" || { echo "COMPILE FAILED: $cmd"; return 1; }
     done < <(grep -E '^xvlog ' "$tcl_file")
 
+    # K to run: requested one, or all of 2/3/4. Elaborate snapshots (serial).
+    local ks; if [ -n "$ksel" ]; then ks="$ksel"; else ks="2 3 4"; fi
+    local k specs=()
+    for k in $ks; do
+        echo "  xelab tb_mlkem_kg_katK_xsim -generic_top KP=$k -s mlkem_kg_k$k --timescale 1ns/1ps"
+        xelab tb_mlkem_kg_katK_xsim -generic_top KP=$k -s mlkem_kg_k$k --timescale 1ns/1ps \
+            || { echo "ELAB FAILED for K=$k"; return 1; }
         # Cases per K: K=2 has 0..4, K=3/4 have 0..2.
         local cases
         if [ "$k" = "2" ]; then cases="0 1 2 3 4"; else cases="0 1 2"; fi
         if [ -n "$csel" ]; then cases="$csel"; fi
-
+        local c
-    echo "  xelab tb_mlkem_kg_katK_xsim -generic_top KP=$k -s mlkem_kg_k$k --timescale 1ns/1ps"
+        for c in $cases; do specs+=("mlkem_kg_k$k:$k:$c"); done
-    xelab tb_mlkem_kg_katK_xsim -generic_top KP=$k -s mlkem_kg_k$k --timescale 1ns/1ps \
-        || { echo "ELAB FAILED for K=$k"; return 1; }
-
-    local fail=0
-    for c in $cases; do
-        local log="/tmp/run_tb_top_k${k}_c${c}.log"
-        echo "  xsim mlkem_kg_k$k -R -testplusarg CASE=$c"
-        echo "========================================" | tee "$log"
-        xsim "mlkem_kg_k$k" -R -testplusarg "CASE=$c" 2>&1 | tee -a "$log"
-        echo "========================================" | tee -a "$log"
-        local pf nf
-        pf=$(grep -oE 'PASS|FAIL' "$log" | tail -1)
-        nf=$(grep -c 'cannot be opened' "$log")
-        echo "    K=$k CASE=$c -> ${pf:-NORESULT}  (file-not-found=$nf, log: $log)"
-        { [ "$pf" = "PASS" ] && [ "$nf" -eq 0 ]; } || fail=1
     done
-    return $fail
+
+    run_xsim_jobs top 'PASS|FAIL' PASS "${specs[@]}"
 }
 
 # ML-KEM Encaps runner. Compiles the 'top' tcl xvlog lines (KeyGen datapath =
@@ -161,31 +215,54 @@ run_enc_selected() {
     xvlog -sv --relax sync_rtl/top/TB/tb_mlkem_enc_katK_xsim.v \
         || { echo "ENC TB COMPILE FAILED"; return 1; }
 
-    # K to run: requested one, or all of 2/3/4.
+    # K to run: requested one, or all of 2/3/4. Elaborate snapshots (serial),
+    # then run all (K,case) in parallel.
     local ks; if [ -n "$ksel" ]; then ks="$ksel"; else ks="2 3 4"; fi
-    local fail=0
+    local k specs=()
     for k in $ks; do
         echo "  xelab tb_mlkem_enc_katK_xsim -generic_top KP=$k -s mlkem_enc_k$k --timescale 1ns/1ps"
         xelab tb_mlkem_enc_katK_xsim -generic_top KP=$k -s mlkem_enc_k$k --timescale 1ns/1ps \
-            || { echo "ELAB FAILED for K=$k"; fail=1; continue; }
+            || { echo "ELAB FAILED for K=$k"; return 1; }
-
-        # Encaps KAT cases per K: 0..2 (vectors enc_k{K}_c{0,1,2}_*).
         local cases="0 1 2"
         if [ -n "$csel" ]; then cases="$csel"; fi
-        for c in $cases; do
+        local c
-            local log="/tmp/run_tb_enc_k${k}_c${c}.log"
+        for c in $cases; do specs+=("mlkem_enc_k$k:$k:$c"); done
-            echo "  xsim mlkem_enc_k$k -R -testplusarg CASE=$c"
-            echo "========================================" | tee "$log"
-            xsim "mlkem_enc_k$k" -R -testplusarg "CASE=$c" 2>&1 | tee -a "$log"
-            echo "========================================" | tee -a "$log"
-            local pf nf
-            pf=$(grep -oE 'PASS \(E7\)|FAIL \(E7\)' "$log" | tail -1)
-            nf=$(grep -c 'cannot be opened' "$log")
-            echo "    K=$k CASE=$c -> ${pf:-NORESULT}  (file-not-found=$nf, log: $log)"
-            { [ "$pf" = "PASS (E7)" ] && [ "$nf" -eq 0 ]; } || fail=1
     done
+
+    run_xsim_jobs enc 'PASS \(E7\)|FAIL \(E7\)' 'PASS (E7)' "${specs[@]}"
+}
+
+# ML-KEM Decaps runner. Same compile basis as enc (top tcl minus KeyGen TB) plus
+# the decaps TB. Result line matches the final-stage PASS tag (D0..D7).
+run_dec_selected() {
+    local tcl_file="$1" ksel="$2" csel="$3"
+    set +e
+
+    rm -rf xsim.dir .Xil
+
+    while read -r cmd; do
+        [[ "$cmd" == *tb_mlkem_kg_katK* ]] && continue
+        eval "$cmd" || { echo "COMPILE FAILED: $cmd"; return 1; }
+    done < <(grep -E '^xvlog ' "$tcl_file")
+
+    echo "  xvlog -sv --relax sync_rtl/top/TB/tb_mlkem_dec_katK_xsim.v"
+    xvlog -sv --relax sync_rtl/top/TB/tb_mlkem_dec_katK_xsim.v \
+        || { echo "DEC TB COMPILE FAILED"; return 1; }
+
+    local ks; if [ -n "$ksel" ]; then ks="$ksel"; else ks="2 3 4"; fi
+    local k specs=()
+    for k in $ks; do
+        echo "  xelab tb_mlkem_dec_katK_xsim -generic_top KP=$k -s mlkem_dec_k$k --timescale 1ns/1ps"
+        xelab tb_mlkem_dec_katK_xsim -generic_top KP=$k -s mlkem_dec_k$k --timescale 1ns/1ps \
+            || { echo "ELAB FAILED for K=$k"; return 1; }
+        local cases="0 1 2"
+        if [ -n "$csel" ]; then cases="$csel"; fi
+        local c
+        for c in $cases; do specs+=("mlkem_dec_k$k:$k:$c"); done
     done
-    return $fail
+
+    # match the highest-stage result line: 'K=.. CASE .. PASS (Dn): ...'
+    run_xsim_jobs dec 'PASS \(D[0-7]\)|FAIL \(D[0-7]\)' 'PASS*' "${specs[@]}"
 }
 
 if [ "$MODULE" = "enc" ]; then
@@ -193,7 +270,13 @@ if [ "$MODULE" = "enc" ]; then
     exit $?
 fi
 
-if [ "$MODULE" = "top" ] && [ -n "$SEL_K" ]; then
+if [ "$MODULE" = "dec" ]; then
+    run_dec_selected "$TCL_FILE" "$SEL_K" "$SEL_CASE"
+    exit $?
+fi
+
+if [ "$MODULE" = "top" ]; then
+    # run_top_selected handles all-K (no SEL_K) or a single K, cases in parallel.
     run_top_selected "$TCL_FILE" "$SEL_K" "$SEL_CASE"
     exit $?
 fi

sync_rtl/comp_decomp/TB/tb_comp_decomp.cpp

@@ -1,125 +0,0 @@
-// tb_comp_decomp.cpp - Verilator C++ testbench for comp_decomp_sync
-//
-// Reads test vectors from a hex file specified by +VECTOR_FILE= plusarg.
-// Each line: "MODE D COEFF" (e.g. "C A 3FF" for compress d=10 coeff=0x3FF).
-// MODE: 'C' for compress, 'D' for decompress.
-// Drives the DUT, waits for valid_o, writes "RESULT: COEFF" to stdout.
-//
-// Clock: 10 ns period. Reset: 2 cycles low. Timeout: 100,000 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <cstdlib>
-#include "Vcomp_decomp_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS    10.0
-#define TIMEOUT_CYCLES   100000
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13; // skip "+VECTOR_FILE="
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Instantiate DUT
-    Vcomp_decomp_sync* dut = new Vcomp_decomp_sync;
-
-    // Initialize
-    dut->clk      = 0;
-    dut->rst_n    = 0;
-    dut->coeff_in = 0;
-    dut->d        = 0;
-    dut->mode     = 0;
-    dut->valid_i  = 0;
-    dut->ready_i  = 0;
-
-    // Reset: 2 cycles low
-    for (int i = 0; i < 4; i++) {
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-    }
-    dut->rst_n = 1;
-
-    // Always ready to receive results
-    dut->ready_i = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-
-    while (std::getline(infile, line)) {
-        // Skip empty lines and comments
-        if (line.empty() || line[0] == '#') continue;
-
-        // Parse: MODE D COEFF
-        std::istringstream iss(line);
-        char mode_char;
-        unsigned int d_val, coeff_val;
-        if (!(iss >> mode_char >> std::hex >> d_val >> coeff_val)) continue;
-
-        if (mode_char == 'C')
-            dut->mode = 0;
-        else if (mode_char == 'D')
-            dut->mode = 1;
-        else
-            continue;
-
-        dut->d        = d_val & 0x1F;
-        dut->coeff_in = coeff_val & 0xFFF;
-        dut->valid_i  = 1;
-
-        // posedge: DUT samples valid_i, pipeline_reg captures data
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        cycle++;
-        dut->valid_i = 0;
-
-        // posedge: pipeline_reg sends result out (valid_o=1)
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        cycle++;
-
-        printf("RESULT: %03X\n", dut->coeff_out & 0xFFF);
-    }
-
-    infile.close();
-    delete dut;
-    return 0;
-}

sync_rtl/mod_add/TB/tb_mod_add.cpp

@@ -1,120 +0,0 @@
-// tb_mod_add.cpp - Verilator C++ testbench for mod_add_sync
-//
-// Reads test vectors from a hex file specified by +VECTOR_FILE= plusarg.
-// Each line: "AAA BBB" (two 12-bit hex operands).
-// Drives the DUT, waits for valid_o, writes "RESULT: CCC" to stdout.
-//
-// Clock: CLK_PERIOD ns period (from defines.vh).
-// Reset: 2 cycles low, then high.
-// Timeout: 100,000 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <cstdlib>
-#include "Vmod_add_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS    10.0
-#define TIMEOUT_CYCLES   100000
-#define Q                3329
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13; // skip "+VECTOR_FILE="
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Instantiate DUT
-    Vmod_add_sync* dut = new Vmod_add_sync;
-
-    // Initialize
-    dut->clk    = 0;
-    dut->rst_n  = 0;
-    dut->a      = 0;
-    dut->b      = 0;
-    dut->valid_i = 0;
-    dut->ready_i = 0;
-
-    // Reset: 2 cycles low
-    for (int i = 0; i < 4; i++) {
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-    }
-    dut->rst_n = 1;
-
-    // Always ready to receive results
-    dut->ready_i = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-    bool waiting_result = false;
-
-    while (std::getline(infile, line)) {
-        // Skip empty lines and comments
-        if (line.empty() || line[0] == '#') continue;
-
-        // Parse hex operands
-        std::istringstream iss(line);
-        unsigned int a_val, b_val;
-        if (!(iss >> std::hex >> a_val >> b_val)) continue;
-
-        dut->a       = a_val & 0xFFF;
-        dut->b       = b_val & 0xFFF;
-        dut->valid_i = 1;
-
-        // posedge: DUT samples valid_i, pipeline_reg captures data, valid_o→1
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        cycle++;
-        dut->valid_i = 0;
-
-        // posedge: pipeline_reg clears valid_o (ready_i=1), but result is
-        // available on sum port right now (combinational from data_r)
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        cycle++;
-
-        printf("RESULT: %03X\n", dut->sum & 0xFFF);
-    }
-
-    infile.close();
-    delete dut;
-    return 0;
-}

sync_rtl/ntt/TB/tb_ntt.cpp

@@ -1,195 +0,0 @@
-// tb_ntt.cpp - Verilator C++ testbench for ntt_sync
-//
-// Reads test vectors from +VECTOR_FILE= plusarg.
-// Format: "MODE COEFF0 COEFF1 ... COEFF255"
-//   MODE: "F" = forward NTT, "I" = inverse NTT
-//   COEFFx: 3-digit hex (12-bit, 000..CFF)
-//
-// Drives DUT with coefficients one per cycle, waits for output,
-// prints "RESULT: COEFF0 COEFF1 ... COEFF255\n" to stdout.
-//
-// Clock: 10ns period. Reset: 2 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <vector>
-#include <cstdlib>
-#include <cstring>
-#include <cstdint>
-#include "Vntt_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS     10.0
-#define TIMEOUT_CYCLES    500000
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-// Toggle clock: both edges + eval (one full cycle)
-static void posedge(Vntt_sync* dut) {
-    dut->clk = 1;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-    dut->clk = 0;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-}
-
-static int hex_char_to_nibble(char c) {
-    if (c >= '0' && c <= '9') return c - '0';
-    if (c >= 'A' && c <= 'F') return c - 'A' + 10;
-    if (c >= 'a' && c <= 'f') return c - 'a' + 10;
-    return 0;
-}
-
-// Parse 3-char hex token to 12-bit value.
-static uint16_t hex3_to_val(const std::string& tok) {
-    uint16_t val = 0;
-    for (size_t i = 0; i < tok.length() && i < 3; i++) {
-        val = (val << 4) | hex_char_to_nibble(tok[i]);
-    }
-    return val & 0xFFF;
-}
-
-// Format 12-bit value as 3-char hex (lowercase for consistency).
-static std::string val_to_hex3(uint16_t val) {
-    char buf[4];
-    snprintf(buf, sizeof(buf), "%03X", val & 0xFFF);
-    return std::string(buf);
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Instantiate DUT
-    Vntt_sync* dut = new Vntt_sync;
-
-    // Initialize
-    dut->clk     = 0;
-    dut->rst_n   = 0;
-    dut->mode    = 0;
-    dut->coeff_in = 0;
-    dut->valid_i = 0;
-    dut->ready_i = 0;
-
-    // Reset: 2 full cycles
-    for (int i = 0; i < 2; i++) posedge(dut);
-    dut->rst_n = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-    int vec_count = 0;
-
-    while (std::getline(infile, line)) {
-        if (line.empty() || line[0] == '#') continue;
-
-        // Parse: MODE COEFF0 COEFF1 ... COEFF255
-        std::istringstream iss(line);
-        std::string mode_str;
-        if (!(iss >> mode_str)) continue;
-
-        int mode_val = 0;
-        if (mode_str == "I") mode_val = 1;
-
-        // Parse 256 coefficients into vector
-        std::vector<uint16_t> input_coeffs(256);
-        std::string tok;
-        int coeff_idx = 0;
-        while (iss >> tok && coeff_idx < 256) {
-            input_coeffs[coeff_idx] = hex3_to_val(tok);
-            coeff_idx++;
-        }
-        if (coeff_idx != 256) {
-            std::cerr << "ERROR: Expected 256 coefficients, got " << coeff_idx
-                      << " (vec " << vec_count << ")" << std::endl;
-            continue;
-        }
-
-        // Set mode
-        dut->mode = mode_val;
-
-        // ---- Load 256 coefficients ----
-        while (!dut->ready_o) {
-            posedge(dut); cycle++;
-            if (cycle > TIMEOUT_CYCLES) goto timeout_err;
-        }
-        for (int i = 0; i < 256; i++) {
-            dut->coeff_in = input_coeffs[i];
-            dut->valid_i = 1;
-            posedge(dut); cycle++;
-            dut->valid_i = 0;
-            if (cycle > TIMEOUT_CYCLES) goto timeout_err;
-        }
-
-        // At this point, the DUT has captured all 256 coeffs and
-        // transitioned to S_COMPUTE_RD (ready_o went low).
-
-        // ---- Wait for valid_o (DUT computing) ----
-        dut->ready_i = 1;
-        while (!dut->valid_o) {
-            posedge(dut);
-            cycle++;
-            if (cycle > TIMEOUT_CYCLES) goto timeout_err;
-        }
-
-        // ---- Read 256 output coefficients ----
-        printf("RESULT: ");
-        for (int i = 0; i < 256; i++) {
-            // Wait for valid_o to be asserted (data is valid NOW)
-            while (!dut->valid_o) {
-                posedge(dut);
-                cycle++;
-                if (cycle > TIMEOUT_CYCLES) goto timeout_err;
-            }
-
-            // Capture coefficient BEFORE consuming posedge
-            uint16_t coeff_val = (uint16_t)(dut->coeff_out & 0xFFF);
-            printf("%s%s", val_to_hex3(coeff_val).c_str(),
-                   (i < 255) ? " " : "");
-
-            // Consume this coefficient: posedge with ready_i=1
-            posedge(dut);
-            cycle++;
-        }
-        printf("\n");
-
-        vec_count++;
-    }
-
-    std::cout << "Processed " << vec_count << " vectors" << std::endl;
-    infile.close();
-    delete dut;
-    return (vec_count > 0) ? 0 : 1;
-
-timeout_err:
-    std::cerr << "ERROR: Timeout at cycle " << cycle
-              << " (vec " << vec_count << ")" << std::endl;
-    infile.close();
-    delete dut;
-    return 1;
-}

sync_rtl/poly_arith/TB/tb_poly_arith.cpp

@@ -1,175 +0,0 @@
-// tb_poly_arith.cpp - Verilator C++ testbench for poly_arith_sync
-//
-// Reads test vectors from a hex file specified by +VECTOR_FILE= plusarg.
-// Each line: "MODE A0 A1 ... A255 B0 B1 ... B255"
-//   MODE: 'A' for add, 'S' for sub
-//   A0..A255: 256 hex coefficients (12-bit, 3 hex digits each)
-//   B0..B255: 256 hex coefficients
-//
-// Feeds 256 (A, B) pairs through the DUT, collects 256 output coeffs,
-// prints one "RESULT: C0 C1 ... C255" line per vector.
-//
-// Clock: 10 ns period (100 MHz).
-// Reset: 2 cycles low, then high.
-// Timeout: 100,000 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <cstdlib>
-#include <vector>
-#include "Vpoly_arith_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS    10.0
-#define TIMEOUT_CYCLES   100000
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-// Helper: toggle clock (full cycle: low->high->low) with eval
-static void posedge(Vpoly_arith_sync* dut) {
-    dut->clk = !dut->clk;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-    dut->clk = !dut->clk;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Instantiate DUT
-    Vpoly_arith_sync* dut = new Vpoly_arith_sync;
-
-    // Initialize
-    dut->clk         = 0;
-    dut->rst_n       = 0;
-    dut->coeff_a_in  = 0;
-    dut->coeff_b_in  = 0;
-    dut->mode        = 0;
-    dut->valid_i     = 0;
-    dut->ready_i     = 0;
-
-    // Reset: 2 cycles low
-    for (int i = 0; i < 4; i++) {
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-    }
-    dut->rst_n = 1;
-
-    // Always ready to receive results
-    dut->ready_i = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-
-    while (std::getline(infile, line)) {
-        // Skip empty lines and comments
-        if (line.empty() || line[0] == '#') continue;
-
-        // Parse: MODE A0..A255 B0..B255 (513 values on one line)
-        std::istringstream iss(line);
-        std::string mode_str;
-        if (!(iss >> mode_str)) continue;
-
-        // Determine mode
-        bool mode_val;
-        if (mode_str == "A" || mode_str == "a") {
-            mode_val = false;
-        } else if (mode_str == "S" || mode_str == "s") {
-            mode_val = true;
-        } else {
-            std::cerr << "ERROR: Unknown mode: " << mode_str << std::endl;
-            continue;
-        }
-
-        dut->mode = mode_val ? 1 : 0;
-
-        // Read 256 A coeffs
-        unsigned int coeff;
-        std::vector<unsigned int> a_coeffs, b_coeffs;
-        for (int i = 0; i < 256; i++) {
-            if (!(iss >> std::hex >> coeff)) {
-                std::cerr << "ERROR: Missing A coeff at index " << i << std::endl;
-                return 1;
-            }
-            a_coeffs.push_back(coeff & 0xFFF);
-        }
-
-        // Read 256 B coeffs
-        for (int i = 0; i < 256; i++) {
-            if (!(iss >> std::hex >> coeff)) {
-                std::cerr << "ERROR: Missing B coeff at index " << i << std::endl;
-                return 1;
-            }
-            b_coeffs.push_back(coeff & 0xFFF);
-        }
-
-        // Feed 256 coefficient pairs and collect results
-        std::vector<unsigned int> results;
-        for (int i = 0; i < 256; i++) {
-            // Drive inputs
-            dut->coeff_a_in = a_coeffs[i];
-            dut->coeff_b_in = b_coeffs[i];
-            dut->valid_i    = 1;
-
-            // Posedge: DUT samples input, pipeline_reg captures data, valid_o→1
-            posedge(dut);
-            dut->valid_i = 0;
-
-            // Read result now (valid_o is high, coeff_out is valid)
-            // Posedge: pipeline_reg clears valid_o (ready_i=1), but result
-            // is available on coeff_out port (combinational from data_r)
-            posedge(dut);
-
-            results.push_back(dut->coeff_out & 0xFFF);
-
-            cycle += 2;
-            if (cycle > TIMEOUT_CYCLES) {
-                std::cerr << "ERROR: Timeout after " << cycle << " cycles" << std::endl;
-                return 1;
-            }
-        }
-
-        // Print result as one space-separated hex line
-        printf("RESULT:");
-        for (int i = 0; i < 256; i++) {
-            printf(" %03X", results[i]);
-        }
-        printf("\n");
-    }
-
-    infile.close();
-    delete dut;
-    return 0;
-}

sync_rtl/poly_mul/TB/tb_poly_mul.cpp

@@ -1,186 +0,0 @@
-// tb_poly_mul.cpp - Verilator C++ testbench for poly_mul_sync
-//
-// Reads test vectors from +VECTOR_FILE= plusarg.
-// Format: one line with 512 space-separated hex values:
-//   A[0] A[1] ... A[255] B[0] B[1] ... B[255]
-// Each value is a 3-digit hex (12-bit).
-//
-// Drives DUT with 256 paired (A,B) coefficients, waits for valid_o,
-// then reads 256 output coefficients via valid/ready handshake.
-// Prints "RESULT: COEFF0 COEFF1 ... COEFF255\n" to stdout.
-//
-// Clock: 10ns period. Reset: 2 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <vector>
-#include <cstdlib>
-#include <cstring>
-#include <cstdint>
-#include "Vpoly_mul_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS     10.0
-#define TIMEOUT_CYCLES    500000
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-// Toggle clock: both edges + eval (one full cycle)
-static void posedge(Vpoly_mul_sync* dut) {
-    dut->clk = 1;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-    dut->clk = 0;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-}
-
-static int hex_char_to_nibble(char c) {
-    if (c >= '0' && c <= '9') return c - '0';
-    if (c >= 'A' && c <= 'F') return c - 'A' + 10;
-    if (c >= 'a' && c <= 'f') return c - 'a' + 10;
-    return 0;
-}
-
-// Parse 3-char hex token to 12-bit value.
-static uint16_t hex3_to_val(const std::string& tok) {
-    uint16_t val = 0;
-    for (size_t i = 0; i < tok.length() && i < 3; i++) {
-        val = (val << 4) | hex_char_to_nibble(tok[i]);
-    }
-    return val & 0xFFF;
-}
-
-// Format 12-bit value as 3-char hex.
-static std::string val_to_hex3(uint16_t val) {
-    char buf[4];
-    snprintf(buf, sizeof(buf), "%03X", val & 0xFFF);
-    return std::string(buf);
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Instantiate DUT
-    Vpoly_mul_sync* dut = new Vpoly_mul_sync;
-
-    // Initialize
-    dut->clk        = 0;
-    dut->rst_n      = 0;
-    dut->coeff_a_in = 0;
-    dut->coeff_b_in = 0;
-    dut->valid_i    = 0;
-    dut->ready_i    = 0;
-
-    // Reset: 2 full cycles
-    for (int i = 0; i < 2; i++) posedge(dut);
-    dut->rst_n = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-    int vec_count = 0;
-
-    while (std::getline(infile, line)) {
-        if (line.empty() || line[0] == '#') continue;
-
-        // Parse: A[0] A[1] ... A[255] B[0] B[1] ... B[255]
-        // Total: 512 hex values, one line
-        std::istringstream iss(line);
-        std::string tok;
-
-        std::vector<uint16_t> input_coeffs(512);
-        int coeff_idx = 0;
-        while (iss >> tok && coeff_idx < 512) {
-            input_coeffs[coeff_idx] = hex3_to_val(tok);
-            coeff_idx++;
-        }
-        if (coeff_idx != 512) {
-            std::cerr << "ERROR: Expected 512 coefficients, got " << coeff_idx
-                      << " (vec " << vec_count << ")" << std::endl;
-            continue;
-        }
-
-        // ---- Load 256 A+B pairs ----
-        while (!dut->ready_o) {
-            posedge(dut); cycle++;
-            if (cycle > TIMEOUT_CYCLES) goto timeout_err;
-        }
-        for (int i = 0; i < 256; i++) {
-            dut->coeff_a_in = input_coeffs[i];
-            dut->coeff_b_in = input_coeffs[256 + i];
-            dut->valid_i    = 1;
-            posedge(dut); cycle++;
-            dut->valid_i    = 0;
-            if (cycle > TIMEOUT_CYCLES) goto timeout_err;
-        }
-
-        // ---- Wait for valid_o (DUT computing) ----
-        dut->ready_i = 1;
-        while (!dut->valid_o) {
-            posedge(dut);
-            cycle++;
-            if (cycle > TIMEOUT_CYCLES) goto timeout_err;
-        }
-
-        // ---- Read 256 output coefficients ----
-        printf("RESULT: ");
-        for (int i = 0; i < 256; i++) {
-            // Wait for valid_o to be asserted (data is valid NOW)
-            while (!dut->valid_o) {
-                posedge(dut);
-                cycle++;
-                if (cycle > TIMEOUT_CYCLES) goto timeout_err;
-            }
-
-            // Capture coefficient BEFORE consuming posedge
-            uint16_t coeff_val = (uint16_t)(dut->coeff_out & 0xFFF);
-            printf("%s%s", val_to_hex3(coeff_val).c_str(),
-                   (i < 255) ? " " : "");
-
-            // Consume this coefficient: posedge with ready_i=1
-            posedge(dut);
-            cycle++;
-        }
-        printf("\n");
-
-        vec_count++;
-    }
-
-    std::cout << "Processed " << vec_count << " vectors" << std::endl;
-    infile.close();
-    delete dut;
-    return (vec_count > 0) ? 0 : 1;
-
-timeout_err:
-    std::cerr << "ERROR: Timeout at cycle " << cycle
-              << " (vec " << vec_count << ")" << std::endl;
-    infile.close();
-    delete dut;
-    return 1;
-}

sync_rtl/rng/TB/tb_rng.cpp

@@ -1,94 +0,0 @@
-// tb_rng.cpp - Verilator C++ testbench for rng_sync
-//
-// Drives valid_i pulses and prints 256-bit LFSR output values.
-// Reads a hex input file to determine how many vectors to generate
-// (one line per vector, content ignored).
-// Prints "RESULT: <64-char hex>" for each output.
-//
-// Clock: 10ns period. Reset: 2 cycles low.
-// Timeout: 100,000 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <cstdio>
-#include "Vrng_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS 10.0
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Count non-empty, non-comment lines to determine vector count
-    int num_vectors = 0;
-    std::string line;
-    while (std::getline(infile, line)) {
-        if (!line.empty() && line[0] != '#')
-            num_vectors++;
-    }
-    infile.close();
-
-    // Instantiate DUT
-    Vrng_sync* dut = new Vrng_sync;
-
-    // Initialize
-    dut->clk     = 0;
-    dut->rst_n   = 0;
-    dut->valid_i = 0;
-    dut->ready_i = 0;
-
-    // Reset: 2 cycles low
-    for (int i = 0; i < 4; i++) {
-        dut->clk = 1; main_time += 5; dut->eval();
-        dut->clk = 0; main_time += 5; dut->eval();
-    }
-    dut->rst_n   = 1;
-    dut->ready_i = 1;
-
-    // Generate vectors
-    for (int n = 0; n < num_vectors; n++) {
-        // Drive valid_i and posedge → LFSR advances, valid_o→1
-        dut->valid_i = 1;
-        dut->clk = 1; main_time += 5; dut->eval();
-        dut->clk = 0; main_time += 5; dut->eval();
-        dut->valid_i = 0;
-
-        // Posedge to consume → valid_o→0
-        dut->clk = 1; main_time += 5; dut->eval();
-        // Print 256-bit result (8 × 32-bit words, MSB first)
-        printf("RESULT: %08X%08X%08X%08X%08X%08X%08X%08X\n",
-               dut->data_o[7], dut->data_o[6], dut->data_o[5], dut->data_o[4],
-               dut->data_o[3], dut->data_o[2], dut->data_o[1], dut->data_o[0]);
-        dut->clk = 0; main_time += 5; dut->eval();
-    }
-
-    delete dut;
-    return 0;
-}

sync_rtl/sample_cbd/TB/tb_sample_cbd.cpp

@@ -1,206 +0,0 @@
-// tb_sample_cbd.cpp - Verilator C++ testbench for sample_cbd_sync
-//
-// Reads test vectors from +VECTOR_FILE= plusarg.
-// Format: "SEED_HEX NONCE_HEX ETA"
-//   SEED_HEX: 64 hex chars (256-bit seed, MSB-first)
-//   NONCE_HEX: 2 hex chars (8-bit nonce)
-//   ETA: "2" or "3" (decimal)
-//
-// Drives DUT with seed, nonce, eta. Waits for valid_o, collects 256
-// coefficients. Prints "RESULT: COEFF_HEX\n" for each coefficient.
-//
-// Clock: 10ns period. Reset: 2 cycles.
-// Timeout: 500000 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <cstdlib>
-#include <cstring>
-#include <cstdint>
-#include "Vsample_cbd_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS     10.0
-#define TIMEOUT_CYCLES    500000
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-// Toggle clock: both edges + eval (one full cycle)
-static void posedge(Vsample_cbd_sync* dut) {
-    dut->clk = !dut->clk;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-    dut->clk = !dut->clk;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-}
-
-static int hex_char_to_nibble(char c) {
-    if (c >= '0' && c <= '9') return c - '0';
-    if (c >= 'A' && c <= 'F') return c - 'A' + 10;
-    if (c >= 'a' && c <= 'f') return c - 'a' + 10;
-    return 0;
-}
-
-// Parse hex string (MSB-first) into 8 x 32-bit words for 256-bit seed.
-// Word 0 = bits[31:0], word 7 = bits[255:224].
-// Hex string: leftmost char = most significant nibble (bits 255:252).
-static void hex_to_256(const std::string& hex, uint32_t data_words[8]) {
-    for (int w = 0; w < 8; w++) data_words[w] = 0;
-
-    int len = (int)hex.length();
-    int nibble_idx = 0;
-    for (int i = len - 1; i >= 0; i--) {
-        char c = hex[i];
-        if (c == ' ' || c == '\t') continue;
-        int nib = hex_char_to_nibble(c);
-        int word_idx = nibble_idx / 8;
-        int shift    = (nibble_idx % 8) * 4;
-        if (word_idx < 8) {
-            data_words[word_idx] |= ((uint32_t)nib << shift);
-        }
-        nibble_idx++;
-    }
-}
-
-// Parse 2-char hex string into an 8-bit value.
-// "FF" → 0xFF, "0A" → 0x0A.
-static uint8_t hex_to_8(const std::string& hex) {
-    int val = 0;
-    for (size_t i = 0; i < hex.length(); i++) {
-        val = (val << 4) | hex_char_to_nibble(hex[i]);
-    }
-    return (uint8_t)(val & 0xFF);
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Instantiate DUT
-    Vsample_cbd_sync* dut = new Vsample_cbd_sync;
-
-    // Initialize
-    dut->clk     = 0;
-    dut->rst_n   = 0;
-    for (int w = 0; w < 8; w++) dut->seed_i[w] = 0;
-    dut->nonce_i = 0;
-    dut->eta_i   = 0;
-    dut->valid_i = 0;
-    dut->ready_i = 0;
-
-    // Reset: 2 full cycles
-    for (int i = 0; i < 2; i++) posedge(dut);
-    dut->rst_n = 1;
-
-    // Consumer always ready
-    dut->ready_i = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-    int vec_count = 0;
-    int total_coeff_count = 0;
-
-    while (std::getline(infile, line)) {
-        if (line.empty() || line[0] == '#') continue;
-
-        // Parse: SEED_HEX NONCE_HEX ETA
-        std::istringstream iss(line);
-        std::string seed_hex, nonce_hex;
-        int eta_val;
-        if (!(iss >> seed_hex >> nonce_hex >> eta_val)) continue;
-        if (seed_hex.length() < 64) continue;
-
-        // Set seed_i (256 bits)
-        uint32_t seed_words[8];
-        hex_to_256(seed_hex, seed_words);
-        for (int w = 0; w < 8; w++) dut->seed_i[w] = seed_words[w];
-
-        // Set nonce_i (8 bits)
-        dut->nonce_i = hex_to_8(nonce_hex);
-
-        // Set eta_i (2'd2 or 2'd3)
-        dut->eta_i = (eta_val == 3) ? 3 : 2;
-
-        // Assert valid_i for one cycle
-        dut->valid_i = 1;
-        posedge(dut);
-        cycle++;
-        dut->valid_i = 0;
-
-        // Wait for 256 coefficients
-        int coeffs_collected = 0;
-        bool timed_out = false;
-
-        while (coeffs_collected < 256) {
-            posedge(dut);
-            cycle++;
-
-            if (cycle > TIMEOUT_CYCLES) {
-                std::cerr << "ERROR: Timeout waiting for coeffs (vec "
-                          << vec_count << ", got " << coeffs_collected
-                          << "/256)" << std::endl;
-                timed_out = true;
-                break;
-            }
-
-            if (dut->valid_o && dut->ready_i) {
-                // Read 12-bit coefficient and print
-                uint32_t coeff = dut->coeff_o & 0xFFF;
-                printf("RESULT: %03X\n", coeff);
-                coeffs_collected++;
-                total_coeff_count++;
-            }
-        }
-
-        if (timed_out) {
-            goto done;
-        }
-
-        // Wait for DUT to return to IDLE before next vector
-        int wait_cycles = 0;
-        while (!dut->ready_o && wait_cycles < 100) {
-            posedge(dut);
-            cycle++;
-            wait_cycles++;
-        }
-
-        vec_count++;
-    }
-
-done:
-    infile.close();
-    delete dut;
-
-    if (vec_count == 0) {
-        std::cerr << "ERROR: No vectors processed" << std::endl;
-        return 1;
-    }
-
-    return 0;
-}

sync_rtl/sample_ntt/TB/tb_sample_ntt.cpp

@@ -1,194 +0,0 @@
-// tb_sample_ntt.cpp - Verilator C++ testbench for sample_ntt_sync
-//
-// Reads test vectors from +VECTOR_FILE= plusarg.
-// Each line: "RHO_HEX K_HEX I_HEX J_HEX"
-//   RHO_HEX: 64 hex chars (32 bytes, MSB-first per byte pair)
-//   K_HEX, I_HEX, J_HEX: single hex digits
-//
-// Drives DUT, waits for 256 coefficients via valid_o handshake,
-// prints "RESULT: CCC" for each (12-bit hex).
-//
-// Clock: 10ns period. Reset: 2 cycles. Timeout: 2,000,000 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <cstdlib>
-#include <cstdint>
-#include <cstring>
-#include "Vsample_ntt_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS     10.0
-#define TIMEOUT_CYCLES    2000000
-#define Q                 3329
-#define N_COEFFS          256
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-static void posedge(Vsample_ntt_sync* dut) {
-    dut->clk = !dut->clk;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-    dut->clk = !dut->clk;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-}
-
-static int hex_char_to_nibble(char c) {
-    if (c >= '0' && c <= '9') return c - '0';
-    if (c >= 'A' && c <= 'F') return c - 'A' + 10;
-    if (c >= 'a' && c <= 'f') return c - 'a' + 10;
-    return 0;
-}
-
-static void parse_rho(const std::string& hex, Vsample_ntt_sync* dut) {
-    for (int w = 0; w < 8; w++) dut->rho_i[w] = 0;
-
-    int byte_count = 0;
-    for (size_t i = 0; i < hex.length() && byte_count < 32; i += 2) {
-        while (i < hex.length() && (hex[i] == ' ' || hex[i] == '\t')) i++;
-        if (i + 1 >= hex.length()) break;
-
-        char high_c = hex[i];
-        char low_c  = hex[i + 1];
-        uint8_t byte_val = (hex_char_to_nibble(high_c) << 4) |
-                            hex_char_to_nibble(low_c);
-
-        int word_idx = byte_count / 4;
-        int byte_off = byte_count % 4;
-        if (word_idx < 8) {
-            dut->rho_i[word_idx] |= ((uint32_t)byte_val << (byte_off * 8));
-        }
-        byte_count++;
-    }
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    Vsample_ntt_sync* dut = new Vsample_ntt_sync;
-
-    // Initialize
-    dut->clk    = 0;
-    dut->rst_n  = 0;
-    for (int i = 0; i < 8; i++) dut->rho_i[i] = 0;
-    dut->k_i    = 0;
-    dut->i_idx  = 0;
-    dut->j_idx  = 0;
-    dut->valid_i = 0;
-    dut->ready_i = 0;
-
-    // Reset: 2 full cycles
-    for (int i = 0; i < 2; i++) posedge(dut);
-    dut->rst_n = 1;
-
-    dut->ready_i = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-    int vec_count = 0;
-
-    while (std::getline(infile, line)) {
-        if (line.empty() || line[0] == '#') continue;
-
-        std::string rho_hex, k_str, i_str, j_str;
-        std::istringstream iss(line);
-        if (!(iss >> rho_hex >> k_str >> i_str >> j_str)) {
-            std::cerr << "ERROR: Malformed input line: " << line << std::endl;
-            continue;
-        }
-
-        if (rho_hex.length() < 64) {
-            std::cerr << "ERROR: RHO_HEX too short" << std::endl;
-            continue;
-        }
-
-        int k_val = 0, i_val = 0, j_val = 0;
-        if (!k_str.empty()) k_val = hex_char_to_nibble(k_str[0]);
-        if (!i_str.empty()) i_val = hex_char_to_nibble(i_str[0]);
-        if (!j_str.empty()) j_val = hex_char_to_nibble(j_str[0]);
-
-        // Set inputs
-        parse_rho(rho_hex, dut);
-        dut->k_i   = k_val & 0x7;
-        dut->i_idx = i_val & 0x3;
-        dut->j_idx = j_val & 0x3;
-        dut->valid_i = 1;
-
-        // Wait for ready_o (DUT must be IDLE)
-        while (!dut->ready_o && cycle < TIMEOUT_CYCLES) {
-            posedge(dut);
-            cycle++;
-        }
-        if (cycle >= TIMEOUT_CYCLES) {
-            std::cerr << "ERROR: Timeout waiting for ready_o (vec "
-                      << vec_count << ")" << std::endl;
-            goto done;
-        }
-
-        // Capture edge
-        posedge(dut);
-        cycle++;
-        dut->valid_i = 0;
-
-        // Wait for and print 256 coefficients
-        int coeff_count = 0;
-        while (coeff_count < N_COEFFS && cycle < TIMEOUT_CYCLES) {
-            while (!dut->valid_o && cycle < TIMEOUT_CYCLES) {
-                posedge(dut);
-                cycle++;
-            }
-            if (cycle >= TIMEOUT_CYCLES) {
-                std::cerr << "ERROR: Timeout waiting for coeff "
-                          << coeff_count << " (vec " << vec_count << ")"
-                          << std::endl;
-                goto done;
-            }
-
-            uint32_t coeff_val = (uint32_t)(dut->coeff_o) & 0xFFF;
-            printf("RESULT: %03X\n", coeff_val);
-
-            posedge(dut);
-            cycle++;
-            coeff_count++;
-        }
-
-        vec_count++;
-    }
-
-done:
-    infile.close();
-    delete dut;
-
-    if (vec_count == 0) {
-        std::cerr << "ERROR: No vectors processed" << std::endl;
-        return 1;
-    }
-
-    return 0;
-}

sync_rtl/sha3/TB/tb_sha3.cpp

@@ -1,196 +0,0 @@
-// tb_sha3.cpp - Verilator C++ testbench for sha3_top
-//
-// Reads test vectors from +VECTOR_FILE=plusarg.
-// Format: "MM DDDD..." (mode hex, then 512-bit message hex)
-//   MM: "00"=G, "01"=H, "10"=J
-//   DDDD...: 128 hex chars representing 512-bit data_i
-//
-// Drives DUT with mode and input, waits for ready_o/valid_o,
-// prints "RESULT: OUTPUT_HEX\n" to stdout.
-//
-// Clock: 10ns period. Reset: 2 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <cstdlib>
-#include <cstring>
-#include <cstdint>
-#include "Vsha3_top.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS     10.0
-#define TIMEOUT_CYCLES    500000
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-// Toggle clock: both edges + eval (one full cycle)
-static void posedge(Vsha3_top* dut) {
-    dut->clk = !dut->clk;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-    dut->clk = !dut->clk;
-    main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-    dut->eval();
-}
-
-static int hex_char_to_nibble(char c) {
-    if (c >= '0' && c <= '9') return c - '0';
-    if (c >= 'A' && c <= 'F') return c - 'A' + 10;
-    if (c >= 'a' && c <= 'f') return c - 'a' + 10;
-    return 0;
-}
-
-// Parse a hex string into Verilator WData words (16 x 32-bit = 512 bits).
-// Hex string is MSB-first (leftmost hex char = bits 511:508).
-// data[0] = bits[31:0], data[15] = bits[511:480].
-static void hex_to_512(const std::string& hex, uint32_t data_words[16]) {
-    for (int w = 0; w < 16; w++) data_words[w] = 0;
-
-    int len = (int)hex.length();
-    // nibble_idx increments for each hex char from RIGHT to LEFT
-    int nibble_idx = 0;
-    for (int i = len - 1; i >= 0; i--) {
-        char c = hex[i];
-        if (c == ' ' || c == '\t') continue;
-        int nib = hex_char_to_nibble(c);
-        int word_idx = nibble_idx / 8;       // 8 nibbles per 32-bit word
-        int shift    = (nibble_idx % 8) * 4; // shift within the word
-        if (word_idx < 16) {
-            data_words[word_idx] |= ((uint32_t)nib << shift);
-        }
-        nibble_idx++;
-    }
-}
-
-// Print hash_o as hex (MSB-first).
-// data[0] = bits[31:0], data[15] = bits[511:480].
-static void print_hex(uint32_t data_words[16], int bits) {
-    int full_words = bits / 32;
-    // Build hex from MSB nibble to LSB nibble
-    for (int w = full_words - 1; w >= 0; w--) {
-        uint32_t val = data_words[w];
-        for (int j = 28; j >= 0; j -= 4) {
-            int nib = (int)((val >> j) & 0xF);
-            printf("%01X", nib);
-        }
-    }
-    printf("\n");
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Instantiate DUT
-    Vsha3_top* dut = new Vsha3_top;
-
-    // Initialize
-    dut->clk     = 0;
-    dut->rst_n   = 0;
-    dut->mode    = 0;
-    for (int w = 0; w < 16; w++) dut->data_i[w] = 0;
-    dut->valid_i = 0;
-    dut->ready_i = 0;
-    // multi-block absorb path disabled for single-block G/H/J tests
-    dut->mb_en     = 0;
-    dut->mb_valid_i = 0;
-    dut->mb_last_i  = 0;
-
-    // Reset: 2 full cycles
-    for (int i = 0; i < 2; i++) posedge(dut);
-    dut->rst_n = 1;
-
-    // Consumer always ready
-    dut->ready_i = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-    int vec_count = 0;
-
-    while (std::getline(infile, line)) {
-        if (line.empty() || line[0] == '#') continue;
-
-        // Parse: MODE_HEX MESSAGE_HEX
-        std::istringstream iss(line);
-        std::string mode_str, data_hex;
-        if (!(iss >> mode_str >> data_hex)) continue;
-        if (mode_str.length() < 2) continue;
-
-        int mode_val = hex_char_to_nibble(mode_str[1]);
-
-        // Set mode
-        dut->mode = mode_val & 0x3;
-
-        // Set data_i from hex string
-        uint32_t data_words[16];
-        hex_to_512(data_hex, data_words);
-        for (int w = 0; w < 16; w++) dut->data_i[w] = data_words[w];
-
-        // Assert valid_i for one cycle
-        dut->valid_i = 1;
-
-        // posedge: DUT samples valid_i, starts keccak_core
-        posedge(dut);
-        cycle++;
-        dut->valid_i = 0;
-
-        // Wait for valid_o (keccak_core takes ~25 cycles)
-        do {
-            posedge(dut);
-            cycle++;
-            if (cycle > TIMEOUT_CYCLES) {
-                std::cerr << "ERROR: Timeout waiting for valid_o (vec " << vec_count << ")" << std::endl;
-                goto done;
-            }
-        } while (!dut->valid_o);
-
-        // Read hash_o and print
-        uint32_t hash_words[16];
-        for (int w = 0; w < 16; w++) hash_words[w] = dut->hash_o[w];
-
-        int out_bits = (mode_val == 0) ? 512 : 256;
-        printf("RESULT: ");
-        print_hex(hash_words, out_bits);
-
-        // One more cycle for valid_o handshake
-        posedge(dut);
-        cycle++;
-        vec_count++;
-    }
-
-done:
-    infile.close();
-    delete dut;
-
-    if (vec_count == 0) {
-        std::cerr << "ERROR: No vectors processed" << std::endl;
-        return 1;
-    }
-
-    return 0;
-}

sync_rtl/storage/TB/tb_storage.cpp

@@ -1,111 +0,0 @@
-// tb_storage.cpp - Verilator C++ testbench for storage (sd_bram top)
-//
-// Reads test vectors from +VECTOR_FILE= hex file.
-// Format: "ADDR DATA" per line (addr in 2-char hex, data in 12-char hex).
-// Writes values via sd_bram, reads back, prints "RESULT: VAL_HEX".
-// s_bram is compiled as rtl_dep.
-//
-// Clock: 10ns period. W=48, D=64, A=6 (default sd_bram parameters).
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <vector>
-#include <cstdint>
-#include "Vsd_bram.h"
-#include "verilated.h"
-
-#define CLK_HALF_PS 5000
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return (double)main_time / 1000.0;
-}
-
-static void tick(Vsd_bram* dut) {
-    dut->clk = 1;
-    main_time += CLK_HALF_PS;
-    dut->eval();
-    dut->clk = 0;
-    main_time += CLK_HALF_PS;
-    dut->eval();
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-            break;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    struct Vec { int addr; uint64_t data; };
-    std::vector<Vec> vectors;
-
-    std::string line;
-    while (std::getline(infile, line)) {
-        if (line.empty() || line[0] == '#') continue;
-        std::istringstream iss(line);
-        int a;
-        uint64_t d;
-        if (!(iss >> std::hex >> a >> d)) continue;
-        if (a < 0 || a > 63) continue;
-        vectors.push_back({a, d & 0xFFFFFFFFFFFFULL});
-    }
-    infile.close();
-
-    if (vectors.empty()) {
-        std::cerr << "ERROR: No valid vectors in file" << std::endl;
-        return 1;
-    }
-
-    Vsd_bram* dut = new Vsd_bram;
-
-    dut->clk     = 0;
-    dut->rd_addr = 0;
-    dut->wr_en   = 0;
-    dut->wr_addr = 0;
-    dut->wr_data = 0;
-    dut->eval();
-    main_time += CLK_HALF_PS;
-    dut->eval();
-
-    // --- WRITE PHASE ---
-    for (size_t i = 0; i < vectors.size(); i++) {
-        dut->wr_en   = 1;
-        dut->wr_addr = vectors[i].addr & 0x3F;
-        dut->wr_data = vectors[i].data & 0xFFFFFFFFFFFFULL;
-        tick(dut);
-    }
-    dut->wr_en   = 0;
-    dut->wr_addr = 0;
-    dut->wr_data = 0;
-    tick(dut);
-
-    // --- READ PHASE ---
-    for (size_t i = 0; i < vectors.size(); i++) {
-        dut->rd_addr = vectors[i].addr & 0x3F;
-        tick(dut);
-        printf("RESULT: %012lX\n", (unsigned long)(dut->rd_data & 0xFFFFFFFFFFFFULL));
-    }
-
-    delete dut;
-    return 0;
-}

sync_rtl/top/TB/gen_decaps_vectors.py

@@ -0,0 +1,80 @@
+#!/usr/bin/env python3
+"""gen_decaps_vectors.py - Emit per-byte Decaps KAT vectors for the XSIM TB.
+
+For ML-KEM-512/768/1024, parse the NIST .rsp and write, per case:
+  dec_k{K}_c{N}_dk.hex  : dk (=sk) bytes, one hex byte per line, byte 0 first
+  dec_k{K}_c{N}_ct.hex  : ct bytes (valid ciphertext), one per line, byte 0 first
+  dec_k{K}_c{N}_ss.hex  : ss bytes (shared secret for valid ct), byte 0 first
+  dec_k{K}_c{N}_ctn.hex : ct_n bytes (corrupted ct -> implicit reject)
+  dec_k{K}_c{N}_ssn.hex : ss_n bytes (shared secret K-bar for the reject path)
+
+The TB streams dk into the design via dk_in_* (routed to dk_pke/ek_pke/h/z by
+region) and ct into c_in_*, runs Decaps, and checks ss:
+  valid ct  -> ss == ss   (c'==c, K' kept)
+  ct_n      -> ss == ss_n (c'!=c, K-bar via J(z||c_n))
+
+Run: python3 gen_decaps_vectors.py [num_cases]
+"""
+
+import os
+import re
+import sys
+
+ML_KEM_R = os.environ.get("ML_KEM_R", os.path.expanduser("~/Dev/ml-kem-r"))
+OUT_DIR = os.path.join(os.path.dirname(__file__), "vectors")
+KATS = {2: "kat_MLKEM_512.rsp", 3: "kat_MLKEM_768.rsp", 4: "kat_MLKEM_1024.rsp"}
+
+
+def parse_kat(path, n):
+    """Return list of dicts {count, sk, ct, ss, ct_n, ss_n} (hex) for first n."""
+    vecs, cur = [], {}
+    with open(path) as f:
+        for line in f:
+            line = line.strip()
+            m = re.match(r"^count\s*=\s*(\d+)$", line)
+            if m:
+                if cur:
+                    vecs.append(cur)
+                if len(vecs) >= n:
+                    break
+                cur = {"count": int(m.group(1))}
+                continue
+            # exact-key match: 'ct =' vs 'ct_n =', 'ss =' vs 'ss_n ='
+            m = re.match(r"^(sk|ct|ss|ct_n|ss_n)\s*=\s*([0-9a-fA-F]+)$", line)
+            if m and cur:
+                cur[m.group(1)] = m.group(2).lower()
+    if cur and len(vecs) < n:
+        vecs.append(cur)
+    return vecs
+
+
+def write_bytes(path, hexstr):
+    """Write hex string as one byte per line (byte 0 = first 2 hex chars)."""
+    with open(path, "w") as f:
+        for i in range(0, len(hexstr), 2):
+            f.write(hexstr[i:i + 2] + "\n")
+
+
+def main():
+    ncases = int(sys.argv[1]) if len(sys.argv) > 1 else 3
+    os.makedirs(OUT_DIR, exist_ok=True)
+    for k, fname in KATS.items():
+        path = os.path.join(ML_KEM_R, "test_data", fname)
+        if not os.path.exists(path):
+            print(f"skip K={k}: {path} not found", file=sys.stderr)
+            continue
+        vecs = parse_kat(path, ncases)
+        for v in vecs:
+            n = v["count"]
+            base = os.path.join(OUT_DIR, f"dec_k{k}_c{n}")
+            write_bytes(f"{base}_dk.hex", v["sk"])
+            write_bytes(f"{base}_ct.hex", v["ct"])
+            write_bytes(f"{base}_ss.hex", v["ss"])
+            write_bytes(f"{base}_ctn.hex", v["ct_n"])
+            write_bytes(f"{base}_ssn.hex", v["ss_n"])
+        print(f"K={k}: wrote {len(vecs)} cases "
+              f"(dk={len(vecs[0]['sk'])//2}B ct={len(vecs[0]['ct'])//2}B)")
+
+
+if __name__ == "__main__":
+    main()

sync_rtl/top/TB/tb_mlkem_dec_katK_xsim.v

@@ -0,0 +1,153 @@
+// tb_mlkem_dec_katK_xsim.v - ML-KEM Decaps vs NIST KAT, parametric K (KP) + CASE.
+// D0 stage: stream dk (=sk) into the design via dk_in_* (routed to
+// dk_pke/ek_pke/h/z by region) and ct via c_in_*, pulse start with op=2, and
+// verify the dk PARSE: H(ek) (dbg_dech_o), z (dbg_decz_o), and round-trip a few
+// ek_pke bytes (dbg_byte sel=0) and dk_pke bytes (sel=1) back out of BRAM.
+//
+// xelab -generic_top KP=2|3|4 ; xsim -testplusarg CASE=n
+//   dk/ct/ss vectors: sync_rtl/top/TB/vectors/dec_k{K}_c{N}_{dk,ct,ss,ctn,ssn}.hex
+`timescale 1ns/1ps
+module tb_mlkem_dec_katK_xsim;
+    parameter KP = 2;
+    localparam DKB = 768*KP + 96;                  // dk (=sk) bytes: 1632/2400/3168
+    localparam EKB = 384*KP + 32;                  // ek_pke bytes within dk
+    localparam DKPB = 384*KP;                      // dk_pke bytes
+    localparam CTB = (KP==4) ? 1568 : (32*(10*KP+4)); // ct bytes: 768/1088/1568
+
+    reg clk=0, rst_n=0, start_i=0;
+    reg [2:0]   k_i;
+    reg [255:0] d_i=0, z_i=0, m_i=0;
+    wire busy_o, done_o;
+    // ek preload port (unused in Decaps; ek_pke comes from dk)
+    reg         ek_in_we=0; reg [10:0] ek_in_addr=0; reg [7:0] ek_in_byte=0;
+    // dk / c input ports
+    reg         dk_in_we=0; reg [11:0] dk_in_addr=0; reg [7:0] dk_in_byte=0;
+    reg         c_in_we=0;  reg [10:0] c_in_addr=0;  reg [7:0] c_in_byte=0;
+    wire [255:0] ss_o;
+    reg  [10:0] dbg_ct_idx_i=0; wire [7:0] dbg_ct_o;
+    reg [3:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
+    reg dbg_byte_sel_i=0; reg [10:0] dbg_byte_idx_i=0; wire [7:0] dbg_byte_o;
+    reg [11:0] dbg_dk_idx_i=0; wire [7:0] dbg_dk_o;
+    wire [255:0] dbg_rho_o, dbg_sigma_o, dbg_r_o, dbg_hek_o;
+    wire [255:0] dbg_mprime_o, dbg_kbar_o, dbg_decz_o, dbg_dech_o;
+
+    mlkem_top dut (
+        .clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(2'd2),
+        .d_i(d_i), .z_i(z_i), .msg_i(m_i), .start_i(start_i),
+        .busy_o(busy_o), .done_o(done_o),
+        .ek_in_we(ek_in_we), .ek_in_addr(ek_in_addr), .ek_in_byte(ek_in_byte),
+        .dk_in_we(dk_in_we), .dk_in_addr(dk_in_addr), .dk_in_byte(dk_in_byte),
+        .c_in_we(c_in_we), .c_in_addr(c_in_addr), .c_in_byte(c_in_byte),
+        .ss_o(ss_o), .dbg_ct_idx_i(dbg_ct_idx_i), .dbg_ct_o(dbg_ct_o),
+        .dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
+        .dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
+        .dbg_dk_idx_i(dbg_dk_idx_i), .dbg_dk_o(dbg_dk_o),
+        .dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o),
+        .dbg_r_o(dbg_r_o), .dbg_hek_o(dbg_hek_o),
+        .dbg_mprime_o(dbg_mprime_o), .dbg_kbar_o(dbg_kbar_o),
+        .dbg_decz_o(dbg_decz_o), .dbg_dech_o(dbg_dech_o)
+    );
+    always #5 clk = ~clk;
+
+    reg [7:0] dk_b [0:DKB-1];
+    reg [7:0] ct_b [0:CTB-1];
+    reg [7:0] ss_b [0:31];
+    integer c, i, j, errors, casenum;
+    reg [8*80-1:0] tag, dkfile, ctfile, ssfile;
+
+    initial begin
+        if (!$value$plusargs("CASE=%d", casenum)) casenum = 0;
+        $sformat(tag, "k%0d", KP);
+        $sformat(dkfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_dk.hex", tag, casenum);
+        $sformat(ctfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_ct.hex", tag, casenum);
+        $sformat(ssfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_ss.hex", tag, casenum);
+        $readmemh(dkfile, dk_b);
+        $readmemh(ctfile, ct_b);
+        $readmemh(ssfile, ss_b);
+        k_i = KP[2:0];
+
+        $display("=== ML-KEM K=%0d Decaps KAT case %0d (D0: load+parse) ===", KP, casenum);
+
+        rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
+
+        // ---- stream dk into the design (1 byte/cycle) ----
+        for (i = 0; i < DKB; i = i + 1) begin
+            dk_in_we = 1'b1; dk_in_addr = i[11:0]; dk_in_byte = dk_b[i];
+            @(posedge clk);
+        end
+        dk_in_we = 1'b0;
+
+        // ---- stream ct into c_in_bram (1 byte/cycle) ----
+        for (i = 0; i < CTB; i = i + 1) begin
+            c_in_we = 1'b1; c_in_addr = i[10:0]; c_in_byte = ct_b[i];
+            @(posedge clk);
+        end
+        c_in_we = 1'b0; @(posedge clk);
+
+        // ---- run Decaps ----
+        start_i=1; @(posedge clk); start_i=0;
+        c=0; while(!done_o && c<2000000) begin @(posedge clk); c=c+1; end
+        if(!done_o) begin $display("FAIL K=%0d case %0d: timeout", KP, casenum); $finish; end
+        $display("=== Decaps D0 done in %0d cyc ===", c);
+
+        verify_d0;
+        $finish;
+    end
+
+    initial begin #120000000; $display("FAIL: global timeout"); $finish; end
+
+    // D0: verify dk parse. H(ek)=dk[768K+32:+32], z=dk[768K+64:+32] captured into
+    // hek_r/z_r (dbg_dech_o/dbg_decz_o). ek_pke=dk[384K:768K+32] in ek_bram
+    // (dbg_byte sel=0), dk_pke=dk[0:384K] in dkp_bram (sel=1).
+    task verify_d0;
+        integer be;
+        reg [7:0] got;
+        begin
+            errors = 0;
+            // H(ek)
+            for (j = 0; j < 32; j = j + 1)
+                if (dbg_dech_o[8*j +: 8] !== dk_b[DKPB + EKB + j]) errors = errors + 1;
+            if (errors == 0) $display("  PASS: H(ek) parsed == dk[768K+32 ..]");
+            else             $display("  FAIL: H(ek) %0d byte mismatches", errors);
+
+            // z
+            be = 0;
+            for (j = 0; j < 32; j = j + 1)
+                if (dbg_decz_o[8*j +: 8] !== dk_b[DKPB + EKB + 32 + j]) be = be + 1;
+            if (be == 0) $display("  PASS: z parsed == dk[768K+64 ..]");
+            else         $display("  FAIL: z %0d byte mismatches", be);
+            errors = errors + be;
+
+            // ek_pke round-trip (every 97th byte to keep it quick)
+            be = 0;
+            for (i = 0; i < EKB; i = i + 97) begin
+                dbg_byte_sel_i = 1'b0; dbg_byte_idx_i = i[10:0];
+                @(posedge clk); @(posedge clk);
+                if (dbg_byte_o !== dk_b[DKPB + i]) begin
+                    if (be < 6) $display("  ekpke[%0d] got=%02x exp=%02x", i, dbg_byte_o, dk_b[DKPB+i]);
+                    be = be + 1;
+                end
+            end
+            if (be == 0) $display("  PASS: ek_pke round-trip (BRAM) == dk[384K ..]");
+            else         $display("  FAIL: ek_pke %0d byte mismatches", be);
+            errors = errors + be;
+
+            // dk_pke round-trip
+            be = 0;
+            for (i = 0; i < DKPB; i = i + 97) begin
+                dbg_byte_sel_i = 1'b1; dbg_byte_idx_i = i[10:0];
+                @(posedge clk); @(posedge clk);
+                if (dbg_byte_o !== dk_b[i]) begin
+                    if (be < 6) $display("  dkpke[%0d] got=%02x exp=%02x", i, dbg_byte_o, dk_b[i]);
+                    be = be + 1;
+                end
+            end
+            if (be == 0) $display("  PASS: dk_pke round-trip (BRAM) == dk[0 ..]");
+            else         $display("  FAIL: dk_pke %0d byte mismatches", be);
+            errors = errors + be;
+
+            if (errors == 0) $display("K=%0d CASE %0d PASS (D0): dk parse OK", KP, casenum);
+            else             $display("K=%0d CASE %0d FAIL (D0): %0d total errors", KP, casenum, errors);
+        end
+    endtask
+endmodule

sync_rtl/top/TB/tb_mlkem_enc_katK_xsim.v

@@ -27,16 +27,19 @@ module tb_mlkem_enc_katK_xsim;
     wire [255:0] dbg_rho_o, dbg_sigma_o, dbg_r_o, dbg_hek_o;
 
     mlkem_top dut (
-        .clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(1'b1),
+        .clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(2'd1),
         .d_i(d_i), .z_i(z_i), .msg_i(m_i), .start_i(start_i),
         .busy_o(busy_o), .done_o(done_o),
         .ek_in_we(ek_in_we), .ek_in_addr(ek_in_addr), .ek_in_byte(ek_in_byte),
+        .dk_in_we(1'b0), .dk_in_addr(12'd0), .dk_in_byte(8'd0),
+        .c_in_we(1'b0), .c_in_addr(11'd0), .c_in_byte(8'd0),
         .ss_o(ss_o), .dbg_ct_idx_i(dbg_ct_idx_i), .dbg_ct_o(dbg_ct_o),
         .dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
         .dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
         .dbg_dk_idx_i(dbg_dk_idx_i), .dbg_dk_o(dbg_dk_o),
         .dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o),
-        .dbg_r_o(dbg_r_o), .dbg_hek_o(dbg_hek_o)
+        .dbg_r_o(dbg_r_o), .dbg_hek_o(dbg_hek_o),
+        .dbg_mprime_o(), .dbg_kbar_o(), .dbg_decz_o(), .dbg_dech_o()
     );
     always #5 clk = ~clk;
 

sync_rtl/top/TB/tb_mlkem_kg_katK_xsim.v

@@ -19,16 +19,19 @@ module tb_mlkem_kg_katK_xsim;
 
     // KMAX defaults to 4 (worst-case sizing); KP selects the runtime k value.
     mlkem_top dut (
-        .clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(1'b0),
+        .clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(2'd0),
         .d_i(d_i), .z_i(z_i), .msg_i(256'd0), .start_i(start_i),
         .busy_o(busy_o), .done_o(done_o),
         .ek_in_we(1'b0), .ek_in_addr(11'd0), .ek_in_byte(8'd0),
+        .dk_in_we(1'b0), .dk_in_addr(12'd0), .dk_in_byte(8'd0),
+        .c_in_we(1'b0), .c_in_addr(11'd0), .c_in_byte(8'd0),
         .ss_o(), .dbg_ct_idx_i(11'd0), .dbg_ct_o(),
         .dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
         .dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
         .dbg_dk_idx_i(dbg_dk_idx_i), .dbg_dk_o(dbg_dk_o),
         .dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o),
-        .dbg_r_o(), .dbg_hek_o()
+        .dbg_r_o(), .dbg_hek_o(),
+        .dbg_mprime_o(), .dbg_kbar_o(), .dbg_decz_o(), .dbg_dech_o()
     );
     always #5 clk = ~clk;
 

sync_rtl/top/TB/vectors/dec_k2_c0_ct.hex

@@ -0,0 +1,768 @@
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sync_rtl/top/TB/vectors/dec_k2_c2_ss.hex

@@ -0,0 +1,32 @@
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sync_rtl/top/TB/vectors/dec_k2_c2_ssn.hex

@@ -0,0 +1,32 @@
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sync_rtl/top/TB/vectors/dec_k3_c0_ss.hex

@@ -0,0 +1,32 @@
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sync_rtl/top/TB/vectors/dec_k3_c0_ssn.hex

@@ -0,0 +1,32 @@
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sync_rtl/top/TB/vectors/dec_k3_c1_ss.hex

@@ -0,0 +1,32 @@
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sync_rtl/top/TB/vectors/dec_k3_c1_ssn.hex

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sync_rtl/top/TB/vectors/dec_k3_c2_ss.hex

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sync_rtl/top/TB/vectors/dec_k3_c2_ssn.hex

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sync_rtl/top/TB/vectors/dec_k4_c0_ss.hex

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sync_rtl/top/TB/vectors/dec_k4_c0_ssn.hex

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sync_rtl/top/TB/vectors/dec_k4_c1_ss.hex

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sync_rtl/top/TB/vectors/dec_k4_c1_ssn.hex

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sync_rtl/top/TB/vectors/dec_k4_c2_ss.hex

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sync_rtl/top/TB/vectors/dec_k4_c2_ssn.hex

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sync_rtl/top/mlkem_top.v

@@ -28,7 +28,7 @@ module mlkem_top #(
     input              clk,
     input              rst_n,
     input  [2:0]       k_i,          // RUNTIME ML-KEM param: 2=512, 3=768, 4=1024
-    input              op_i,          // 0 = KeyGen, 1 = Encaps (captured at start_i)
+    input  [1:0]       op_i,          // 0=KeyGen, 1=Encaps, 2=Decaps (captured at start_i)
     input  [255:0]     d_i,          // KeyGen seed d (byte 0 in d_i[7:0])
     input  [255:0]     z_i,          // implicit-rejection seed z
     input  [255:0]     msg_i,        // Encaps message m (byte 0 in msg_i[7:0])
@@ -41,6 +41,21 @@ module mlkem_top #(
     input              ek_in_we,     // write one ek byte (only honored in ST_IDLE for Encaps preload)
     input  [10:0]      ek_in_addr,   // ek byte address 0..ek_bytes-1
     input  [7:0]       ek_in_byte,   // ek byte value
+    // Decaps dk input: stream dk bytes (=sk, 768K+96) into the design before
+    // start_i with op_i=2. The load logic routes each byte by region:
+    //   [0,384K)            -> dk_pke (dkp_bram)   = s_hat encoding
+    //   [384K, 768K+32)     -> ek_pke (ek_bram)    = t_hat encoding || rho
+    //   [768K+32, 768K+64)  -> H(ek)  (hek_r)
+    //   [768K+64, 768K+96)  -> z      (z_r)
+    input              dk_in_we,     // write one dk byte (ST_IDLE Decaps preload)
+    input  [11:0]      dk_in_addr,   // dk byte address 0..(768K+96)-1
+    input  [7:0]       dk_in_byte,   // dk byte value
+    // Decaps ciphertext input: stream c bytes (=ct) into c_in_bram before
+    // start_i. Kept separate from ct_bram so the computed c' can be compared
+    // against the original c (and J(z||c) can read c) without aliasing.
+    input              c_in_we,      // write one c byte (ST_IDLE Decaps preload)
+    input  [10:0]      c_in_addr,    // c byte address 0..ct_bytes-1
+    input  [7:0]       c_in_byte,    // c byte value
     // Encaps shared secret output (= K), valid at done_o
     output [255:0]     ss_o,
     // Encaps ciphertext readback tap: ct byte by index 0..ct_bytes-1
@@ -65,7 +80,12 @@ module mlkem_top #(
     output [255:0]     dbg_sigma_o,
     // Encaps debug taps: r (G high half) and H(ek)
     output [255:0]     dbg_r_o,
-    output [255:0]     dbg_hek_o
+    output [255:0]     dbg_hek_o,
+    // Decaps debug taps: m' (Decrypt output), K-bar (J output), parsed z/h.
+    output [255:0]     dbg_mprime_o,
+    output [255:0]     dbg_kbar_o,
+    output [255:0]     dbg_decz_o,   // parsed z (dk[768K+64:+32])
+    output [255:0]     dbg_dech_o    // parsed H(ek) (dk[768K+32:+32])
 );
 
     localparam Q = `Q;   // 3329
@@ -82,15 +102,28 @@ module mlkem_top #(
     wire [5:0] slot_t_rt = kk_rt + {1'b0, k_r} + {1'b0, k_r};  // t_hat base = kk+2k
     wire [11:0] ek_bytes_rt = 12'd384 * {9'b0, k_r} + 12'd32;  // 800/1184/1568
     wire [11:0] dk_bytes_rt = 12'd384 * {9'b0, k_r};            // 768/1152/1536
+    // full dk = dk_pke(dk_bytes) || ek(ek_bytes) || H(ek)(32) || z(32). Region
+    // boundaries (used by Decaps dk load routing and dk readback).
+    wire [11:0] dk_ek_end   = dk_bytes_rt + ek_bytes_rt;        // ek_pke region end
+    wire [11:0] dk_hek_end  = dk_ek_end + 12'd32;               // H(ek) region end
+    // LOAD-TIME boundaries: dk is streamed in BEFORE start_i, so k_r is not yet
+    // captured. Route the dk load by the LIVE k_i input instead of k_r.
+    wire [11:0] dkp_bytes_ld = 12'd384 * {9'b0, k_i};                 // 768/1152/1536
+    wire [11:0] ek_bytes_ld  = 12'd384 * {9'b0, k_i} + 12'd32;        // 800/1184/1568
+    wire [11:0] dk_ek_end_ld = dkp_bytes_ld + ek_bytes_ld;           // ek_pke region end
+    wire [11:0] dk_hek_end_ld= dk_ek_end_ld + 12'd32;                // H(ek) region end
     // H(ek) block count = ceil((ek_bytes+1)/136): 6/9/12 for k=2/3/4 (table)
     wire [3:0] h_nblk_rt = (k_r == 3'd2) ? 4'd6 : (k_r == 3'd3) ? 4'd9 : 4'd12;
     wire [11:0] h_last_rt = {6'b0, h_nblk_rt} * 12'd136 - 12'd1;  // final padded byte index
 
     // ---- Encaps runtime params ----
-    reg          op_r;             // 0=KeyGen 1=Encaps (captured at start)
+    reg  [1:0]   op_r;             // 0=KeyGen 1=Encaps 2=Decaps (captured at start)
-    reg  [255:0] m_r;              // Encaps message m (captured at start)
+    reg  [255:0] m_r;              // Encaps message m (captured at start); Decaps reuses for m'
     reg  [255:0] ss_r;             // Encaps shared secret K (= G output low half)
     reg  [255:0] r_r;              // Encaps PRF seed r (= G output high half)
+    // ---- Decaps runtime params (parsed from dk during load) ----
+    reg  [255:0] z_r;              // implicit-rejection seed z (dk tail), captured at load
+    reg  [255:0] kbar_r;           // K-bar = J(z||c) (D5)
     // FIPS 203: eta2 = 2 for all parameter sets.
     wire [1:0]  eta2_rt = 2'd2;
     // Compression params: (du,dv) = (10,4) for k=2/3, (11,5) for k=4.
@@ -100,6 +133,7 @@ module mlkem_top #(
     wire [11:0] c1_bytes_rt = 12'd32 * {7'b0, du_rt} * {9'b0, k_r};  // 640/960/1408
     wire [11:0] c2_bytes_rt = 12'd32 * {7'b0, dv_rt};                 // 128/128/160
     wire [11:0] ct_bytes_rt = c1_bytes_rt + c2_bytes_rt;             // 768/1088/1568
+    wire [11:0] ct_bytes_rt = c1_bytes_rt + c2_bytes_rt;             // 768/1088/1568
     assign ss_o = ss_r;
 
     // ---- E1: rho-load + byteDecode12 bookkeeping ----
@@ -145,6 +179,23 @@ module mlkem_top #(
     assign ct_rd_addr = dbg_ct_idx_i;
     assign dbg_ct_o   = ct_rd_data;
 
+    // ---- c_in_bram: Decaps input ciphertext c (<=1568 B). Preloaded via
+    // c_in_* in ST_IDLE. Kept separate from ct_bram (which holds the computed
+    // c') so D7 can compare c' vs c and D5 J(z||c) can read c. Read port is
+    // muxed (D5 J-feed / D7 compare); for D0 only the load write path exists.
+    wire [10:0] cin_rd_addr;
+    wire [7:0]  cin_rd_data;
+    reg  [10:0] cin_rd_addr_r;       // D5/D7 read address (tied 0 until then)
+    sd_bram #(.W(8), .D(2048), .A(11)) u_c_in_bram (
+        .clk(clk),
+        .rd_addr(cin_rd_addr), .rd_data(cin_rd_data),
+        .wr_en(c_in_we), .wr_addr(c_in_addr), .wr_data(c_in_byte)
+    );
+    assign cin_rd_addr = cin_rd_addr_r;
+    /* verilator lint_off UNUSEDSIGNAL */
+    wire [7:0] cin_rd_data_unused = cin_rd_data;   // consumed in D5/D7
+    /* verilator lint_on UNUSEDSIGNAL */
+
     // ================================================================
     // Polynomial storage, sized for KMAX (worst case). Runtime k uses a
     // sub-range. Slot layout (each slot = 256 coeffs):
@@ -330,26 +381,39 @@ module mlkem_top #(
     reg  [7:0]  ek_wd, dkp_wd;
 
     // ek BRAM write port: KeyGen ST_E drives ek_we/ek_wa/ek_wd; Encaps preloads
-    // ek from the external ek_in_* port (TB streams ek=pk before start_i). The
+    // ek from the external ek_in_* port (TB streams ek=pk before start_i). Decaps
-    // two never overlap (preload happens in ST_IDLE before an Encaps run).
+    // routes the dk's ek_pke region (dk[384K:768K+32]) here at load time. The
-    wire        ek_we_mux = ek_in_we ? 1'b1       : ek_we;
+    // three never overlap (preloads happen in ST_IDLE before a run).
-    wire [10:0] ek_wa_mux = ek_in_we ? ek_in_addr : ek_wa;
+    wire        dk_ld_ekpke = dk_in_we && (dk_in_addr >= dkp_bytes_ld)
-    wire [7:0]  ek_wd_mux = ek_in_we ? ek_in_byte : ek_wd;
+                                       && (dk_in_addr <  dk_ek_end_ld);  // ek_pke region
+    wire        dk_ld_dkpke = dk_in_we && (dk_in_addr <  dkp_bytes_ld);  // dk_pke region
+    wire [10:0] dk_ek_off   = (dk_in_addr - dkp_bytes_ld);               // offset within ek
+    wire        ek_we_mux = ek_in_we   ? 1'b1       :
+                            dk_ld_ekpke ? 1'b1       : ek_we;
+    wire [10:0] ek_wa_mux = ek_in_we   ? ek_in_addr :
+                            dk_ld_ekpke ? dk_ek_off  : ek_wa;
+    wire [7:0]  ek_wd_mux = ek_in_we   ? ek_in_byte :
+                            dk_ld_ekpke ? dk_in_byte : ek_wd;
 
     sd_bram #(.W(8), .D(2048), .A(11)) u_ek_bram (
         .clk(clk),
         .rd_addr(ek_rd_addr), .rd_data(ek_rd_data),
         .wr_en(ek_we_mux), .wr_addr(ek_wa_mux), .wr_data(ek_wd_mux)
     );
+    // dk_pke BRAM write port: KeyGen ST_E (s_hat byteEncode) drives dkp_we/wa/wd;
+    // Decaps routes the dk's dk_pke region (dk[0:384K]) here at load time. The
+    // two never overlap (preload in ST_IDLE before a Decaps run).
+    wire        dkp_we_mux = dk_ld_dkpke ? 1'b1                 : dkp_we;
+    wire [10:0] dkp_wa_mux = dk_ld_dkpke ? dk_in_addr[10:0]     : dkp_wa;
+    wire [7:0]  dkp_wd_mux = dk_ld_dkpke ? dk_in_byte           : dkp_wd;
     sd_bram #(.W(8), .D(2048), .A(11)) u_dkp_bram (
         .clk(clk),
         .rd_addr(dkp_rd_addr), .rd_data(dkp_rd_data),
-        .wr_en(dkp_we), .wr_addr(dkp_wa), .wr_data(dkp_wd)
+        .wr_en(dkp_we_mux), .wr_addr(dkp_wa_mux), .wr_data(dkp_wd_mux)
     );
 
-    // full dk = dk_pke(dk_bytes) || ek(ek_bytes) || H(ek)(32) || z(32)
+    // full dk = dk_pke(dk_bytes) || ek(ek_bytes) || H(ek)(32) || z(32).
-    wire [11:0] dk_ek_end  = dk_bytes_rt + ek_bytes_rt;   // ek region end
+    // (dk_ek_end / dk_hek_end declared near the top with the other size wires.)
-    wire [11:0] dk_hek_end = dk_ek_end + 12'd32;           // H(ek) region end
 
     // Debug-region selects for dk readback (combinational region decode).
     wire dbgdk_in_dkp = (dbg_dk_idx_i < dk_bytes_rt);
@@ -390,6 +454,8 @@ module mlkem_top #(
     localparam ST_ENC_V    = 5'd17; // v = INTT(sum t_hat o y_hat) + e2 + mu
     localparam ST_ENC_C2   = 5'd18; // Compress_dv + byteEncode_dv -> ct c2
     localparam ST_ENC_E2MV = 5'd19; // relocate e2 bank_t[0] -> bank_a[E2_ASLOT]
+    // ---- Decaps states ----
+    localparam ST_DEC_LOAD = 5'd20; // dk/c already streamed in; parse/settle (D0)
     localparam ST_DONE   = 5'd31;
 
     reg [4:0]   st, st_next;
@@ -418,6 +484,11 @@ module mlkem_top #(
     assign dbg_sigma_o = sigma_r;
     assign dbg_r_o     = r_r;
     assign dbg_hek_o   = hek_r;
+    // Decaps taps: m' reuses m_r (Decrypt writes it), z/h parsed from dk at load.
+    assign dbg_mprime_o = m_r;
+    assign dbg_kbar_o   = kbar_r;
+    assign dbg_decz_o   = z_r;
+    assign dbg_dech_o   = hek_r;   // Decaps parses dk's H(ek) into hek_r at load
 
     // ---- sha3_top in G mode: data_i = {K_byte, d} (d byte0 in [7:0]) ----
     reg          sha3_valid;
@@ -897,7 +968,11 @@ module mlkem_top #(
     always @(*) begin
         st_next = st;
         case (st)
-            ST_IDLE: if (start_i) st_next = op_i ? ST_ENC_H : ST_G;
+            ST_IDLE: if (start_i) st_next = (op_i == 2'd2) ? ST_DEC_LOAD :
+                                            (op_i == 2'd1) ? ST_ENC_H    : ST_G;
+            // D0: settle after dk/c parse, then (D1+) proceed to Decrypt. For now
+            // ST_DEC_LOAD just lands in DONE so the load/parse can be dbg-checked.
+            ST_DEC_LOAD: st_next = ST_DONE;
             ST_G:    if (sha3_vo) st_next = ST_A;
             ST_A:    if (a_pair >= kk_rt) st_next = ST_C;
             ST_C:    if (c_poly >= {1'b0, k_r, 1'b0}) st_next = ST_N;
@@ -927,7 +1002,7 @@ module mlkem_top #(
         if (!rst_n) begin
             st         <= ST_IDLE;
             k_r        <= 3'd0;
-            op_r       <= 1'b0;
+            op_r       <= 2'd0;
             m_r        <= 256'd0;
             ss_r       <= 256'd0;
             r_r        <= 256'd0;
@@ -1024,6 +1099,9 @@ module mlkem_top #(
             h_mblast   <= 1'b0;
             h_ack      <= 1'b0;
             hek_r      <= 256'd0;
+            z_r        <= 256'd0;
+            kbar_r     <= 256'd0;
+            cin_rd_addr_r <= 11'd0;
             h_blk      <= 3'd0;
             h_byte     <= 8'd0;
             h_phase    <= 2'd0;
@@ -1043,11 +1121,12 @@ module mlkem_top #(
             em_we  <= 1'b0;    // e2-relocate bank_a write default low (E6)
 
             // Kick off when entering from IDLE: KeyGen starts G; Encaps captures
-            // op/m and arms the H(ek) machinery (ST_ENC_H reuses the ST_H FSM).
+            // op/m and arms the H(ek) machinery (ST_ENC_H reuses the ST_H FSM);
+            // Decaps captures op (dk/c already streamed; z/h captured at load).
             if (st == ST_IDLE && start_i) begin
                 k_r  <= k_i;                // capture runtime ML-KEM param
                 op_r <= op_i;
-                if (op_i) begin
+                if (op_i == 2'd1) begin
                     m_r      <= msg_i;      // capture Encaps message
                     // arm H(ek) (same fields the ST_E->ST_H arming sets)
                     h_blk    <= 3'd0;
@@ -1057,11 +1136,25 @@ module mlkem_top #(
                     h_mblast <= 1'b0;
                     h_ack    <= 1'b1;       // ready to consume final digest
                     h_wb_vld <= 1'b0;
+                end else if (op_i == 2'd2) begin
+                    // Decaps: dk_pke/ek_pke already in BRAM; z/H(ek) captured into
+                    // z_r/hek_r during load (below). Nothing else to arm in D0.
                 end else begin
                     sha3_valid <= 1'b1;
                     sha3_ack   <= 1'b1;
                 end
             end
+
+            // Decaps dk load: capture the H(ek) and z byte regions into registers
+            // as they stream in (the dk_pke/ek_pke regions go to BRAM via the
+            // write muxes). Byte i within a region lands in [8i +: 8]. Uses the
+            // LIVE k_i boundaries (k_r not yet captured during preload).
+            if (dk_in_we) begin
+                if (dk_in_addr >= dk_ek_end_ld && dk_in_addr < dk_hek_end_ld)
+                    hek_r[(dk_in_addr - dk_ek_end_ld)*8 +: 8] <= dk_in_byte;   // H(ek)
+                else if (dk_in_addr >= dk_hek_end_ld)
+                    z_r[(dk_in_addr - dk_hek_end_ld)*8 +: 8]  <= dk_in_byte;   // z
+            end
             // Drop valid once accepted
             if (sha3_valid && sha3_ready) sha3_valid <= 1'b0;
 

test_framework/config.json

@@ -1,12 +0,0 @@
-{
-  "verilator": {
-    "path": "verilator",
-    "compile_args": ["-Wall", "--cc", "--build", "--timing", "--exe"]
-  },
-  "clock_period_ns": 10.0,
-  "timeout_cycles": 100000,
-  "rtl_root": "sync_rtl",
-  "vector_root": "test_framework/modules/{module}/vectors",
-  "report_root": "test_framework/reports",
-  "keep_vectors": false
-}

test_framework/lib/reporter.py

@@ -1,130 +0,0 @@
-"""reporter.py - Formats and displays test results."""
-
-import os
-import time
-from datetime import datetime
-
-
-class Reporter:
-    """Formats test results for terminal and HTML output."""
-
-    # ANSI color codes
-    GREEN = '\033[92m'
-    RED = '\033[91m'
-    YELLOW = '\033[93m'
-    CYAN = '\033[96m'
-    RESET = '\033[0m'
-    BOLD = '\033[1m'
-
-    def __init__(self, report_dir: str = 'test_framework/reports'):
-        self.report_dir = report_dir
-        os.makedirs(report_dir, exist_ok=True)
-
-    def print_summary(self, results: dict, total_elapsed: float = 0.0) -> bool:
-        """Print formatted test summary to terminal.
-
-        Args:
-            results: Dict of module_name -> module_results.
-            total_elapsed: Total elapsed time in seconds.
-
-        Returns:
-            bool: True if all tests passed.
-        """
-        total_pass = 0
-        total_fail = 0
-        all_pass = True
-
-        print()
-        print(f"{self.BOLD}{'='*60}{self.RESET}")
-        print(f"{self.BOLD}  TEST RESULTS{self.RESET}")
-        print(f"{self.BOLD}{'='*60}{self.RESET}")
-
-        for module_name, module_result in results.items():
-            status = module_result.get('status', 'UNKNOWN')
-            num_pass = module_result.get('pass', 0)
-            num_fail = module_result.get('fail', 0)
-            elapsed = module_result.get('elapsed', 0.0)
-            total_pass += num_pass
-            total_fail += num_fail
-
-            if status == 'PASS':
-                color = self.GREEN
-                icon = '✓'
-            elif status == 'FAIL':
-                color = self.RED
-                icon = '✗'
-                all_pass = False
-            else:
-                color = self.YELLOW
-                icon = '?'
-                all_pass = False
-
-            print(f"  {color}{icon} {module_name}{self.RESET}: "
-                  f"{num_pass} pass, {num_fail} fail, "
-                  f"{elapsed:.2f}s")
-
-        print(f"{self.BOLD}{'='*60}{self.RESET}")
-        total = total_pass + total_fail
-        if all_pass:
-            print(f"  {self.GREEN}{self.BOLD}ALL TESTS PASSED{self.RESET} "
-                  f"({total_pass}/{total} vectors, {total_elapsed:.2f}s)")
-        else:
-            print(f"  {self.RED}{self.BOLD}SOME TESTS FAILED{self.RESET} "
-                  f"({total_pass}/{total} pass, {total_fail}/{total} fail, "
-                  f"{total_elapsed:.2f}s)")
-        print()
-
-        # Write HTML report
-        self._write_html_report(results, total_elapsed)
-        return all_pass
-
-    def _write_html_report(self, results: dict, total_elapsed: float) -> None:
-        """Write an HTML test report."""
-        timestamp = datetime.now().strftime('%Y%m%d_%H%M%S')
-        report_path = os.path.join(self.report_dir, f'report_{timestamp}.html')
-
-        total_pass = sum(r.get('pass', 0) for r in results.values())
-        total_fail = sum(r.get('fail', 0) for r in results.values())
-        all_pass = total_fail == 0
-
-        rows = ''
-        for module_name, module_result in results.items():
-            status = module_result.get('status', 'UNKNOWN')
-            color = '#4CAF50' if status == 'PASS' else '#F44336'
-            rows += f'''
-            <tr>
-                <td>{module_name}</td>
-                <td style="color:{color}">{status}</td>
-                <td>{module_result.get('pass', 0)}</td>
-                <td>{module_result.get('fail', 0)}</td>
-                <td>{module_result.get('elapsed', 0):.2f}s</td>
-            </tr>'''
-
-        html = f'''<!DOCTYPE html>
-<html>
-<head>
-    <title>ML-KEM Test Report</title>
-    <style>
-        body {{ font-family: monospace; background: #1e1e1e; color: #d4d4d4;
-               padding: 20px; }}
-        h1 {{ color: {'#4CAF50' if all_pass else '#F44336'}; }}
-        table {{ border-collapse: collapse; width: 100%; }}
-        th, td {{ border: 1px solid #444; padding: 8px; text-align: left; }}
-        th {{ background: #333; }}
-    </style>
-</head>
-<body>
-    <h1>{'ALL TESTS PASSED' if all_pass else 'SOME TESTS FAILED'}</h1>
-    <p>Generated: {timestamp}<br>
-    Total: {total_pass + total_fail} vectors ({total_pass} pass, {total_fail} fail)<br>
-    Elapsed: {total_elapsed:.2f}s</p>
-    <table>
-        <tr><th>Module</th><th>Status</th><th>Pass</th><th>Fail</th><th>Time</th></tr>
-        {rows}
-    </table>
-</body>
-</html>'''
-
-        with open(report_path, 'w') as f:
-            f.write(html)
-        print(f"  Report saved to: {report_path}")

test_framework/lib/result_checker.py

@@ -1,45 +0,0 @@
-"""result_checker.py - Compares simulation output against expected values."""
-
-
-def check_results(got: list[str], expected_file: str) -> tuple[int, int]:
-    """Compare Verilator output against expected values.
-
-    Args:
-        got: List of result strings from simulation (hex values).
-        expected_file: Path to file containing expected hex values, one per line.
-
-    Returns:
-        tuple[int, int]: (num_pass, num_fail).
-    """
-    # Read expected values
-    expected = []
-    try:
-        with open(expected_file, 'r') as f:
-            for line in f:
-                line = line.strip()
-                if line and not line.startswith('#'):
-                    expected.append(line)
-    except FileNotFoundError:
-        print(f"[ERROR] Expected file not found: {expected_file}")
-        return (0, len(got))
-
-    num_pass = 0
-    num_fail = 0
-
-    max_len = max(len(got), len(expected))
-
-    for i in range(max_len):
-        got_val = got[i].upper() if i < len(got) else 'MISSING'
-        exp_val = expected[i].upper() if i < len(expected) else 'MISSING'
-
-        if got_val == exp_val:
-            num_pass += 1
-        else:
-            num_fail += 1
-            if num_fail <= 5:  # Only show first 5 failures
-                print(f"  MISMATCH[{i}]: got={got_val}, expected={exp_val}")
-
-    if num_fail > 5:
-        print(f"  ... and {num_fail - 5} more mismatches")
-
-    return (num_pass, num_fail)

test_framework/lib/sim_controller.py

@@ -1,134 +0,0 @@
-"""sim_controller.py - Verilator simulation controller.
-
-Handles Verilator compilation and execution of RTL testbenches.
-"""
-
-import subprocess
-import os
-import time
-
-
-class SimController:
-    """Controls Verilator compilation and simulation."""
-
-    def __init__(self, config: dict):
-        """Initialize with test framework configuration.
-
-        Args:
-            config: The loaded config.json dict.
-        """
-        self.config = config
-        self.verilator_path = config.get('verilator', {}).get('path', 'verilator')
-        self.compile_args = config.get('verilator', {}).get('compile_args', [])
-
-    def compile(self, top_module: str, rtl_files: list[str], tb_cpp: str,
-                work_dir: str, inc_dirs: list[str] = None) -> str:
-        """Compile RTL with Verilator and return path to executable.
-
-        Args:
-            top_module: Name of the top-level Verilog module.
-            rtl_files: List of Verilog source file paths.
-            tb_cpp: Path to C++ testbench file.
-            work_dir: Working directory for compilation output (-Mdir).
-            inc_dirs: List of include directories for `include directives.
-
-        Returns:
-            Path to the compiled executable.
-
-        Raises:
-            RuntimeError: If Verilator is not found or compilation fails.
-        """
-        os.makedirs(work_dir, exist_ok=True)
-
-        # Build verilator command
-        cmd = [self.verilator_path]
-        cmd.extend(self.compile_args)
-        cmd.extend(['--top-module', top_module])
-        # No explicit -std= flag; let Verilator use its default (C++14+)
-        if inc_dirs:
-            for d in inc_dirs:
-                cmd.append(f'+incdir+{d}')
-        cmd.extend(rtl_files)
-        cmd.append(tb_cpp)
-        cmd.extend(['-Mdir', work_dir])
-
-        try:
-            result = subprocess.run(
-                cmd,
-                capture_output=True,
-                text=True,
-                timeout=120,
-                cwd=os.getcwd()
-            )
-        except subprocess.TimeoutExpired:
-            raise RuntimeError("Verilator compilation timed out.")
-        except FileNotFoundError:
-            raise RuntimeError(
-                f"Verilator not found at '{self.verilator_path}'."
-            )
-
-        if result.returncode != 0:
-            tail = result.stderr[-800:] if result.stderr else '(no stderr)'
-            raise RuntimeError(f"Verilator compilation failed:\n{tail}")
-
-        # Executable is at <work_dir>/V<top_module>
-        executable = os.path.join(work_dir, f'V{top_module}')
-        if not os.path.exists(executable):
-            raise RuntimeError(
-                f"Compilation succeeded but executable not found: {executable}"
-            )
-        return executable
-
-    def run(self, executable: str, vector_file: str,
-            timeout_s: int = 30) -> dict:
-        """Run the compiled simulation executable.
-
-        Args:
-            executable: Path to the compiled executable.
-            vector_file: Path to the hex vector file.
-            timeout_s: Timeout in seconds.
-
-        Returns:
-            dict with keys: success, results, elapsed, stderr.
-        """
-        if not os.path.exists(executable):
-            return {
-                'success': False,
-                'results': [],
-                'elapsed': 0.0,
-                'stderr': f'Executable not found: {executable}'
-            }
-
-        start_time = time.time()
-        try:
-            result = subprocess.run(
-                [executable, f'+VECTOR_FILE={vector_file}'],
-                capture_output=True,
-                text=True,
-                timeout=timeout_s
-            )
-            elapsed = time.time() - start_time
-
-            # Parse stdout for "RESULT: XXX" lines
-            results = []
-            for line in result.stdout.splitlines():
-                line = line.strip()
-                if line.startswith('RESULT:'):
-                    hex_val = line.split(':', 1)[1].strip()
-                    results.append(hex_val)
-
-            success = result.returncode == 0 and len(results) > 0
-            return {
-                'success': success,
-                'results': results,
-                'elapsed': elapsed,
-                'stderr': result.stderr
-            }
-        except subprocess.TimeoutExpired:
-            elapsed = time.time() - start_time
-            return {
-                'success': False,
-                'results': [],
-                'elapsed': elapsed,
-                'stderr': 'Simulation timed out.'
-            }

test_framework/lib/test_runner.py

@@ -1,243 +0,0 @@
-"""test_runner.py - Main test engine.
-
-Discovers modules, loads test plans, generates vectors, runs simulations,
-and collects results.
-"""
-
-import os
-import json
-import time
-import importlib.util
-import sys
-from pathlib import Path
-
-from .sim_controller import SimController
-from .result_checker import check_results
-
-
-class TestRunner:
-    """Main test engine for the ML-KEM RTL test framework."""
-
-    def __init__(self, config_path: str = 'test_framework/config.json'):
-        """Initialize with configuration.
-
-        Args:
-            config_path: Path to config.json.
-        """
-        self.project_root = os.path.dirname(os.path.dirname(
-            os.path.dirname(os.path.abspath(__file__))))
-        self.config_path = os.path.join(self.project_root, config_path)
-        with open(self.config_path) as f:
-            self.config = json.load(f)
-        self.sim = SimController(self.config)
-        self.modules_dir = os.path.join(self.project_root,
-                                        'test_framework', 'modules')
-        self.rtl_root = os.path.join(self.project_root,
-                                     self.config.get('rtl_root', 'sync_rtl'))
-
-    def discover_modules(self) -> dict[str, dict]:
-        """Scan test_framework/modules/*/test_plan.json and return plans.
-
-        Returns:
-            dict of module_name -> test_plan.
-        """
-        modules = {}
-        if not os.path.isdir(self.modules_dir):
-            return modules
-
-        for entry in os.listdir(self.modules_dir):
-            mod_dir = os.path.join(self.modules_dir, entry)
-            plan_path = os.path.join(mod_dir, 'test_plan.json')
-            if os.path.isdir(mod_dir) and os.path.exists(plan_path):
-                with open(plan_path) as f:
-                    plan = json.load(f)
-                modules[entry] = plan
-        return modules
-
-    def _get_rtl_files(self, plan: dict) -> list[str]:
-        """Resolve RTL source file paths from a test plan.
-
-        Args:
-            plan: Test plan dict with 'rtl_top' and optional 'rtl_deps'.
-
-        Returns:
-            List of absolute paths: deps first, then top.
-        """
-        rtl_top = os.path.join(self.project_root, plan['rtl_top'])
-        rtl_deps = [os.path.join(self.project_root, d)
-                    for d in plan.get('rtl_deps', [])]
-        return rtl_deps + [rtl_top]
-
-    def run_module(self, module_name: str, quick: bool = False,
-                   single_case: str = None) -> dict:
-        """Run all test cases for a module.
-
-        Args:
-            module_name: Name of the module to test.
-            quick: If True, reduce vector count for faster testing.
-            single_case: If set, only run this case ID.
-
-        Returns:
-            dict with keys: pass, fail, cases, elapsed, status.
-        """
-        modules = self.discover_modules()
-        if module_name not in modules:
-            return {
-                'pass': 0, 'fail': 0, 'cases': {},
-                'elapsed': 0.0, 'status': 'NOT_FOUND',
-                'error': f'Module "{module_name}" not found'
-            }
-
-        plan = modules[module_name]
-        mod_dir = os.path.join(self.modules_dir, module_name)
-        vectors_dir = os.path.join(mod_dir, 'vectors')
-        work_dir = os.path.join(mod_dir, 'obj_dir')
-        os.makedirs(vectors_dir, exist_ok=True)
-
-        # Import module's gen_vectors.py
-        gen_path = os.path.join(mod_dir, 'gen_vectors.py')
-        if not os.path.exists(gen_path):
-            return {
-                'pass': 0, 'fail': 0, 'cases': {},
-                'elapsed': 0.0, 'status': 'ERROR',
-                'error': f'gen_vectors.py not found for {module_name}'
-            }
-
-        spec = importlib.util.spec_from_file_location(
-            f'{module_name}_gen', gen_path)
-        gen_module = importlib.util.module_from_spec(spec)
-        sys.modules[f'{module_name}_gen'] = gen_module
-        spec.loader.exec_module(gen_module)
-
-        # Find generator class
-        generator = None
-        for name in dir(gen_module):
-            obj = getattr(gen_module, name)
-            if (isinstance(obj, type) and
-                    hasattr(obj, 'generate_one') and
-                    hasattr(obj, 'write_hex_file') and
-                    name != 'VectorGenerator'):
-                generator = obj()
-                break
-
-        if generator is None:
-            return {
-                'pass': 0, 'fail': 0, 'cases': {},
-                'elapsed': 0.0, 'status': 'ERROR',
-                'error': f'No generator class found in {gen_path}'
-            }
-
-        # Resolve RTL files and top module name
-        rtl_files = self._get_rtl_files(plan)
-        tb_cpp = os.path.join(self.project_root, plan['tb_cpp'])
-
-        # Top module name derived from rtl_top filename (strip .v)
-        top_module = os.path.basename(plan['rtl_top']).replace('.v', '')
-
-        # Compile once for the module
-        print(f"\n  Compiling {module_name} with Verilator...")
-        start_time = time.time()
-
-        try:
-            executable = self.sim.compile(
-                top_module=top_module,
-                rtl_files=rtl_files,
-                tb_cpp=tb_cpp,
-                work_dir=work_dir,
-                inc_dirs=[self.project_root]
-            )
-        except RuntimeError as e:
-            return {
-                'pass': 0, 'fail': 0, 'cases': {},
-                'elapsed': time.time() - start_time,
-                'status': 'COMPILE_ERROR',
-                'error': str(e)
-            }
-
-        case_results = {}
-        total_pass = 0
-        total_fail = 0
-
-        for case in plan.get('cases', []):
-            case_id = case['id']
-
-            # Filter by single case
-            if single_case and case_id != single_case:
-                continue
-
-            num_vectors = case.get('num_vectors', 10)
-            if quick:
-                num_vectors = max(1, num_vectors // 5)
-
-            params = case.get('params', {})
-            print(f"  Case [{case_id}]: {case.get('description', '')} "
-                  f"({num_vectors} vectors)")
-
-            # Generate vectors
-            vectors = []
-            for i in range(num_vectors):
-                vec = generator.generate_one(params)
-                vectors.append(vec)
-
-            # Write input vectors hex file
-            input_file = os.path.join(vectors_dir, f'{case_id}_input.hex')
-            generator.write_hex_file(vectors, input_file)
-
-            # Write expected output hex file
-            expected_file = os.path.join(vectors_dir, f'{case_id}_expected.hex')
-            generator.write_expected_file(vectors, expected_file)
-
-            # Run simulation
-            timeout_s = plan.get('timeout_s', 30)
-            run_result = self.sim.run(executable, input_file, timeout_s)
-
-            if not run_result['success']:
-                case_results[case_id] = {
-                    'pass': 0, 'fail': num_vectors,
-                    'elapsed': run_result['elapsed'],
-                    'error': run_result.get('stderr', 'Simulation failed')
-                }
-                total_fail += num_vectors
-                continue
-
-            # Compare results
-            tolerance = case.get('tolerance', 'bit_exact')
-            if tolerance == 'bit_exact':
-                num_pass, num_fail = check_results(
-                    run_result['results'], expected_file)
-            else:
-                # Delegate to generator for custom comparison
-                if hasattr(generator, 'compare_results'):
-                    compare_ok = generator.compare_results(
-                        run_result['results'], expected_file)
-                    num_pass = num_vectors if compare_ok else 0
-                    num_fail = 0 if compare_ok else num_vectors
-                else:
-                    num_pass, num_fail = check_results(
-                        run_result['results'], expected_file)
-
-            case_results[case_id] = {
-                'pass': num_pass,
-                'fail': num_fail,
-                'elapsed': run_result['elapsed']
-            }
-            total_pass += num_pass
-            total_fail += num_fail
-
-            # Clean up vectors unless keep_vectors is true
-            if not self.config.get('keep_vectors', False):
-                try:
-                    os.remove(input_file)
-                    os.remove(expected_file)
-                except OSError:
-                    pass
-
-        elapsed = time.time() - start_time
-
-        return {
-            'pass': total_pass,
-            'fail': total_fail,
-            'cases': case_results,
-            'elapsed': elapsed,
-            'status': 'PASS' if total_fail == 0 else 'FAIL'
-        }

test_framework/lib/vector_gen.py

@@ -1,61 +0,0 @@
-"""vector_gen.py - Base class for vector generators.
-
-Each module provides a gen_vectors.py that subclasses VectorGenerator.
-The generate_one() method is abstract and must be overridden.
-The write_hex_file() method writes vectors as hex-formatted files.
-"""
-
-import os
-from abc import ABC, abstractmethod
-
-
-class VectorGenerator(ABC):
-    """Base class for test vector generators."""
-
-    @abstractmethod
-    def generate_one(self, params: dict) -> dict:
-        """Generate a single test vector.
-
-        Args:
-            params: Module-specific parameters for vector generation.
-
-        Returns:
-            dict with 'input' and 'expected' keys, each containing a dict
-            of signal_name -> value.
-        """
-        ...
-
-    def write_hex_file(self, vectors: list[dict], filepath: str) -> None:
-        """Write vectors to a hex file.
-
-        Subclasses should override this to match their module's input format.
-        Default: writes each vector on one line, hex values separated by spaces.
-
-        Args:
-            vectors: List of result dicts from generate_one().
-            filepath: Path to write the hex file.
-        """
-        os.makedirs(os.path.dirname(filepath), exist_ok=True)
-        with open(filepath, 'w') as f:
-            for v in vectors:
-                # Default: write input values as space-separated hex
-                inputs = v.get('input', {})
-                hex_vals = [format(val, 'X') for val in inputs.values()]
-                f.write(' '.join(hex_vals) + '\n')
-
-    def write_expected_file(self, vectors: list[dict], filepath: str) -> None:
-        """Write expected results to a hex file.
-
-        Subclasses should override this to match their module's expected format.
-        Default: writes each expected value on one line.
-
-        Args:
-            vectors: List of result dicts from generate_one().
-            filepath: Path to write the expected hex file.
-        """
-        os.makedirs(os.path.dirname(filepath), exist_ok=True)
-        with open(filepath, 'w') as f:
-            for v in vectors:
-                expected = v.get('expected', {})
-                hex_vals = [format(val, 'X') for val in expected.values()]
-                f.write(' '.join(hex_vals) + '\n')

test_framework/modules/comp_decomp/gen_vectors.py

@@ -1,119 +0,0 @@
-"""gen_vectors.py - Test vector generator for comp_decomp module.
-
-Generates (mode, d, coeff) input tuples and computes expected
-compress/decompress results matching the Python reference implementation.
-Uses round-half-up (round(2.5)=3, round(3.5)=4).
-"""
-
-import os
-import random
-import sys
-
-sys.path.insert(0, os.path.join(os.path.dirname(__file__), '..', '..', 'lib'))
-
-from vector_gen import VectorGenerator
-
-Q = 3329  # ML-KEM prime modulus
-
-
-def round_customize(a: float) -> int:
-    """Round-half-up: round(2.5)=3, round(3.5)=4.
-    
-    Matches the reference implementation in de_compress.py.
-    """
-    tmp = int(a) + 0.5
-    if a >= tmp:
-        return int(a) + 1
-    else:
-        return int(a)
-
-
-def compress(z_q: int, q: int, d: int) -> int:
-    """Compress coefficient: round((2^d / q) * z_q) mod 2^d."""
-    _2d = 2 ** d
-    return round_customize((_2d / q) * z_q) % _2d
-
-
-def decompress(z_d: int, q: int, d: int) -> int:
-    """Decompress coefficient: round((q / 2^d) * z_d)."""
-    _2d = 2 ** d
-    return round_customize((q / _2d) * z_d)
-
-
-class CompDecompVectorGenerator(VectorGenerator):
-    """Generates test vectors for the comp_decomp_sync module."""
-
-    def generate_one(self, params: dict) -> dict:
-        """Generate a single (mode, d, coeff) test vector.
-
-        Args:
-            params: dict with 'mode' ('compress'/'decompress') and 'd' (int).
-
-        Returns:
-            dict with 'input' and 'expected' keys.
-        """
-        mode = params.get('mode', 'compress')
-        d = params.get('d', 10)
-
-        if mode == 'compress':
-            coeff = random.randint(0, Q - 1)
-            result = compress(coeff, Q, d)
-        else:
-            coeff = random.randint(0, (2 ** d) - 1)
-            result = decompress(coeff, Q, d)
-
-        return {
-            'input': {'mode': mode, 'd': d, 'coeff': coeff},
-            'expected': {'result': result}
-        }
-
-    def write_hex_file(self, vectors: list[dict], filepath: str) -> None:
-        """Write input vectors as 'MODE D COEFF' format.
-
-        MODE: 'C' for compress, 'D' for decompress.
-        D and COEFF are hex-encoded.
-
-        Example: 'C A 3FF' for compress with d=10, coeff=0x3FF.
-        """
-        os.makedirs(os.path.dirname(filepath), exist_ok=True)
-        with open(filepath, 'w') as f:
-            for v in vectors:
-                inp = v['input']
-                mode_char = 'C' if inp['mode'] == 'compress' else 'D'
-                d_val = inp['d']
-                coeff_val = inp['coeff']
-                f.write(f'{mode_char} {d_val:X} {coeff_val:03X}\n')
-
-    def write_expected_file(self, vectors: list[dict], filepath: str) -> None:
-        """Write expected output as zero-padded 3-digit hex values.
-
-        One value per line matching the %03X format in the testbench.
-        """
-        os.makedirs(os.path.dirname(filepath), exist_ok=True)
-        with open(filepath, 'w') as f:
-            for v in vectors:
-                result = v['expected']['result']
-                f.write(f'{result:03X}\n')
-
-    def compare_results(self, got: list[str], expected_file: str) -> bool:
-        """Compare RTL output against expected values.
-
-        Args:
-            got: List of hex result strings from simulation.
-            expected_file: Path to expected hex file.
-
-        Returns:
-            bool: True if all results match.
-        """
-        with open(expected_file, 'r') as f:
-            expected = [line.strip() for line in f
-                        if line.strip() and not line.startswith('#')]
-
-        if len(got) != len(expected):
-            return False
-
-        for i, (g, e) in enumerate(zip(got, expected)):
-            if g.upper() != e.upper():
-                return False
-
-        return True

test_framework/modules/comp_decomp/test_plan.json

@@ -1,66 +0,0 @@
-{
-  "module": "comp_decomp",
-  "rtl_top": "sync_rtl/comp_decomp/comp_decomp_sync.v",
-  "rtl_deps": ["sync_rtl/common/pipeline_reg.v"],
-  "tb_cpp": "sync_rtl/comp_decomp/TB/tb_comp_decomp.cpp",
-  "simulator": "verilator",
-  "timeout_s": 30,
-  "cases": [
-    {
-      "id": "compress_du10",
-      "description": "Compress with du=10 (ML-KEM-512/768)",
-      "params": {"mode": "compress", "d": 10},
-      "num_vectors": 20,
-      "tolerance": "bit_exact"
-    },
-    {
-      "id": "compress_dv4",
-      "description": "Compress with dv=4 (ML-KEM-512/768)",
-      "params": {"mode": "compress", "d": 4},
-      "num_vectors": 20,
-      "tolerance": "bit_exact"
-    },
-    {
-      "id": "decompress_du10",
-      "description": "Decompress with du=10",
-      "params": {"mode": "decompress", "d": 10},
-      "num_vectors": 10,
-      "tolerance": "bit_exact"
-    },
-    {
-      "id": "decompress_dv4",
-      "description": "Decompress with dv=4",
-      "params": {"mode": "decompress", "d": 4},
-      "num_vectors": 10,
-      "tolerance": "bit_exact"
-    },
-    {
-      "id": "compress_du11",
-      "description": "Compress with du=11 (ML-KEM-1024)",
-      "params": {"mode": "compress", "d": 11},
-      "num_vectors": 20,
-      "tolerance": "bit_exact"
-    },
-    {
-      "id": "compress_dv5",
-      "description": "Compress with dv=5 (ML-KEM-1024)",
-      "params": {"mode": "compress", "d": 5},
-      "num_vectors": 20,
-      "tolerance": "bit_exact"
-    },
-    {
-      "id": "decompress_du11",
-      "description": "Decompress with du=11 (ML-KEM-1024)",
-      "params": {"mode": "decompress", "d": 11},
-      "num_vectors": 10,
-      "tolerance": "bit_exact"
-    },
-    {
-      "id": "decompress_dv5",
-      "description": "Decompress with dv=5 (ML-KEM-1024)",
-      "params": {"mode": "decompress", "d": 5},
-      "num_vectors": 10,
-      "tolerance": "bit_exact"
-    }
-  ]
-}

test_framework/modules/mlkem_keygen/golden/c000_Ahat_0_0.hex

@@ -1,256 +0,0 @@
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test_framework/modules/mlkem_keygen/golden/c000_Ahat_0_1.hex

@@ -1,256 +0,0 @@
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test_framework/modules/mlkem_keygen/golden/c000_Ahat_1_0.hex

@@ -1,256 +0,0 @@
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test_framework/modules/mlkem_keygen/golden/c000_ek.hex

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