diff --git a/create_project.tcl b/create_project.tcl
new file mode 100644
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--- /dev/null
+++ b/create_project.tcl
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+# create_project.tcl — 自动创建 Vivado 工程，添加所有 RTL 源文件和 testbench
+#
+# Usage:
+#   cd ~/Dev/mlkem
+#   vivado -mode batch -source create_project.tcl
+#
+# Or in Vivado Tcl Console:
+#   source create_project.tcl
+
+set PROJECT_NAME  mlkem
+set PROJECT_DIR   [file normalize [file dirname [info script]]]
+
+# Create project (simulation-only, no FPGA part needed)
+create_project -force ${PROJECT_NAME} ${PROJECT_DIR}/vivado_prj
+
+# Set top-level testbench
+set_property top tb_mlkem_top_xsim [current_fileset -simset]
+set_property target_simulator XSim [current_project]
+
+# ── Common infrastructure ──
+read_verilog -sv [glob ${PROJECT_DIR}/sync_rtl/common/*.v]
+
+# ── SHA3 / Keccak ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_round.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/keccak_core.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3/sha3_top.v
+
+# ── SHA3 Chain (shared variant for top-level integration) ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sha3_chain/sha3_chain_top_shared.v
+
+# ── RNG ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/rng/rng_sync.v
+
+# ── NTT ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/zeta_rom.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/barrett_mul.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/butterfly_unit.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/ntt/ntt_core.v
+
+# ── Polynomial Arithmetic ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_arith/poly_arith_sync.v
+
+# ── Polynomial Multiplication ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_zeta_rom.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/basecase_mul.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/poly_mul/poly_mul_sync.v
+
+# ── Sampling ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_cbd/sample_cbd_sync_shared.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
+
+# ── Compression & Modular Arithmetic ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/comp_decomp/comp_decomp_sync.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/mod_add/mod_add_sync.v
+
+# ── Storage (BRAM) ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/s_bram.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/storage/sd_bram.v
+
+# ── Top-level Integration ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/keccak_arbiter.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v
+
+# ── Testbench ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_top_xsim.v
+
+# ── Include path for `include directives ──
+set_property include_dirs ${PROJECT_DIR} [current_fileset -simset]
+
+# ── Simulation settings ──
+set_property -name {xsim.simulate.runtime} -value {all} -objects [get_filesets sim_1]
+set_property -name {xsim.elaborate.xelab.more_options} -value {--timescale 1ns/1ps} -objects [get_filesets sim_1]
+
+# Save project
+puts "========================================"
+puts " Project created: ${PROJECT_DIR}/vivado_prj/${PROJECT_NAME}.xpr"
+puts " Run simulation:"
+puts "   launch_simulation"
+puts "   run all"
+puts "========================================"