chore(tb): remove Verilator TBs + framework; parallelize XSIM runs
Verilator is no longer used (all verification is via Vivado XSIM). Remove: - 10 per-module tb_*.cpp Verilator testbenches - the entire test_framework/ Verilator harness (lib/, run_all.py, config.json, per-module test_plan.json/gen_vectors.py, golden vectors, reports) - stale specs: verilator-conventions.md, test_framework/structure.md (index.md updated to drop the Verilator entry) Parallelize run_tb.sh K x case execution (modules stay serial): - new run_xsim_jobs helper: compile+elaborate once (serial, populates the shared xsim.dir), then run each (K,case) xsim in its own private workdir with a COPY of xsim.dir (~1MB) so concurrent same-snapshot runs don't clobber each other's runtime logs. Each workdir symlinks the repo sync_rtl tree so the TB's repo-relative $readmemh vector paths resolve. - top/enc/dec runners refactored to build a (snapshot:K:case) spec list and hand it to run_xsim_jobs; ordered PASS/FAIL summary + per-job /tmp logs preserved. Bare './run_tb.sh top' now also takes the parallel path. Speedup (20 cores): top full sweep 2:11 -> 0:51 (~2.6x), ~320% CPU. Verified: top (11) / enc (9) / dec (9) all PASS; missing-vector runs still fail (file-not-found guard -> exit 1).
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// tb_storage.cpp - Verilator C++ testbench for storage (sd_bram top)
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//
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// Reads test vectors from +VECTOR_FILE= hex file.
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// Format: "ADDR DATA" per line (addr in 2-char hex, data in 12-char hex).
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// Writes values via sd_bram, reads back, prints "RESULT: VAL_HEX".
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// s_bram is compiled as rtl_dep.
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//
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// Clock: 10ns period. W=48, D=64, A=6 (default sd_bram parameters).
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <sstream>
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#include <vector>
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#include <cstdint>
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#include "Vsd_bram.h"
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#include "verilated.h"
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#define CLK_HALF_PS 5000
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static vluint64_t main_time = 0;
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double sc_time_stamp() {
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return (double)main_time / 1000.0;
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}
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static void tick(Vsd_bram* dut) {
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dut->clk = 1;
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main_time += CLK_HALF_PS;
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dut->eval();
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dut->clk = 0;
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main_time += CLK_HALF_PS;
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dut->eval();
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv);
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const char* vector_file = NULL;
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for (int i = 1; i < argc; i++) {
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std::string arg(argv[i]);
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if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
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vector_file = argv[i] + 13;
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break;
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}
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}
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if (!vector_file) {
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std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
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return 1;
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}
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std::ifstream infile(vector_file);
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if (!infile.is_open()) {
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std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
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return 1;
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}
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struct Vec { int addr; uint64_t data; };
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std::vector<Vec> vectors;
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std::string line;
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while (std::getline(infile, line)) {
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if (line.empty() || line[0] == '#') continue;
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std::istringstream iss(line);
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int a;
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uint64_t d;
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if (!(iss >> std::hex >> a >> d)) continue;
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if (a < 0 || a > 63) continue;
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vectors.push_back({a, d & 0xFFFFFFFFFFFFULL});
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}
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infile.close();
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if (vectors.empty()) {
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std::cerr << "ERROR: No valid vectors in file" << std::endl;
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return 1;
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}
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Vsd_bram* dut = new Vsd_bram;
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dut->clk = 0;
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dut->rd_addr = 0;
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dut->wr_en = 0;
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dut->wr_addr = 0;
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dut->wr_data = 0;
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dut->eval();
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main_time += CLK_HALF_PS;
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dut->eval();
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// --- WRITE PHASE ---
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for (size_t i = 0; i < vectors.size(); i++) {
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dut->wr_en = 1;
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dut->wr_addr = vectors[i].addr & 0x3F;
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dut->wr_data = vectors[i].data & 0xFFFFFFFFFFFFULL;
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tick(dut);
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}
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dut->wr_en = 0;
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dut->wr_addr = 0;
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dut->wr_data = 0;
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tick(dut);
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// --- READ PHASE ---
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for (size_t i = 0; i < vectors.size(); i++) {
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dut->rd_addr = vectors[i].addr & 0x3F;
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tick(dut);
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printf("RESULT: %012lX\n", (unsigned long)(dut->rd_data & 0xFFFFFFFFFFFFULL));
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}
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delete dut;
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return 0;
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}
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