chore(tb): remove Verilator TBs + framework; parallelize XSIM runs
Verilator is no longer used (all verification is via Vivado XSIM). Remove: - 10 per-module tb_*.cpp Verilator testbenches - the entire test_framework/ Verilator harness (lib/, run_all.py, config.json, per-module test_plan.json/gen_vectors.py, golden vectors, reports) - stale specs: verilator-conventions.md, test_framework/structure.md (index.md updated to drop the Verilator entry) Parallelize run_tb.sh K x case execution (modules stay serial): - new run_xsim_jobs helper: compile+elaborate once (serial, populates the shared xsim.dir), then run each (K,case) xsim in its own private workdir with a COPY of xsim.dir (~1MB) so concurrent same-snapshot runs don't clobber each other's runtime logs. Each workdir symlinks the repo sync_rtl tree so the TB's repo-relative $readmemh vector paths resolve. - top/enc/dec runners refactored to build a (snapshot:K:case) spec list and hand it to run_xsim_jobs; ordered PASS/FAIL summary + per-job /tmp logs preserved. Bare './run_tb.sh top' now also takes the parallel path. Speedup (20 cores): top full sweep 2:11 -> 0:51 (~2.6x), ~320% CPU. Verified: top (11) / enc (9) / dec (9) all PASS; missing-vector runs still fail (file-not-found guard -> exit 1).
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// tb_sha3.cpp - Verilator C++ testbench for sha3_top
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//
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// Reads test vectors from +VECTOR_FILE=plusarg.
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// Format: "MM DDDD..." (mode hex, then 512-bit message hex)
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// MM: "00"=G, "01"=H, "10"=J
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// DDDD...: 128 hex chars representing 512-bit data_i
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//
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// Drives DUT with mode and input, waits for ready_o/valid_o,
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// prints "RESULT: OUTPUT_HEX\n" to stdout.
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//
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// Clock: 10ns period. Reset: 2 cycles.
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <sstream>
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#include <cstdlib>
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#include <cstring>
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#include <cstdint>
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#include "Vsha3_top.h"
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#include "verilated.h"
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#define CLK_PERIOD_NS 10.0
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#define TIMEOUT_CYCLES 500000
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static vluint64_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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// Toggle clock: both edges + eval (one full cycle)
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static void posedge(Vsha3_top* dut) {
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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}
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static int hex_char_to_nibble(char c) {
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if (c >= '0' && c <= '9') return c - '0';
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if (c >= 'A' && c <= 'F') return c - 'A' + 10;
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if (c >= 'a' && c <= 'f') return c - 'a' + 10;
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return 0;
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}
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// Parse a hex string into Verilator WData words (16 x 32-bit = 512 bits).
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// Hex string is MSB-first (leftmost hex char = bits 511:508).
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// data[0] = bits[31:0], data[15] = bits[511:480].
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static void hex_to_512(const std::string& hex, uint32_t data_words[16]) {
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for (int w = 0; w < 16; w++) data_words[w] = 0;
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int len = (int)hex.length();
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// nibble_idx increments for each hex char from RIGHT to LEFT
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int nibble_idx = 0;
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for (int i = len - 1; i >= 0; i--) {
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char c = hex[i];
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if (c == ' ' || c == '\t') continue;
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int nib = hex_char_to_nibble(c);
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int word_idx = nibble_idx / 8; // 8 nibbles per 32-bit word
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int shift = (nibble_idx % 8) * 4; // shift within the word
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if (word_idx < 16) {
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data_words[word_idx] |= ((uint32_t)nib << shift);
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}
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nibble_idx++;
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}
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}
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// Print hash_o as hex (MSB-first).
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// data[0] = bits[31:0], data[15] = bits[511:480].
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static void print_hex(uint32_t data_words[16], int bits) {
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int full_words = bits / 32;
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// Build hex from MSB nibble to LSB nibble
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for (int w = full_words - 1; w >= 0; w--) {
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uint32_t val = data_words[w];
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for (int j = 28; j >= 0; j -= 4) {
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int nib = (int)((val >> j) & 0xF);
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printf("%01X", nib);
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}
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}
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printf("\n");
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv);
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// Parse +VECTOR_FILE= plusarg
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const char* vector_file = NULL;
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for (int i = 1; i < argc; i++) {
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std::string arg(argv[i]);
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if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
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vector_file = argv[i] + 13;
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}
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}
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if (!vector_file) {
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std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
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return 1;
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}
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std::ifstream infile(vector_file);
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if (!infile.is_open()) {
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std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
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return 1;
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}
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// Instantiate DUT
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Vsha3_top* dut = new Vsha3_top;
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// Initialize
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dut->clk = 0;
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dut->rst_n = 0;
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dut->mode = 0;
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for (int w = 0; w < 16; w++) dut->data_i[w] = 0;
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dut->valid_i = 0;
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dut->ready_i = 0;
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// multi-block absorb path disabled for single-block G/H/J tests
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dut->mb_en = 0;
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dut->mb_valid_i = 0;
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dut->mb_last_i = 0;
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// Reset: 2 full cycles
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for (int i = 0; i < 2; i++) posedge(dut);
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dut->rst_n = 1;
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// Consumer always ready
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dut->ready_i = 1;
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std::string line;
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vluint64_t cycle = 0;
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int vec_count = 0;
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while (std::getline(infile, line)) {
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if (line.empty() || line[0] == '#') continue;
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// Parse: MODE_HEX MESSAGE_HEX
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std::istringstream iss(line);
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std::string mode_str, data_hex;
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if (!(iss >> mode_str >> data_hex)) continue;
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if (mode_str.length() < 2) continue;
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int mode_val = hex_char_to_nibble(mode_str[1]);
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// Set mode
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dut->mode = mode_val & 0x3;
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// Set data_i from hex string
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uint32_t data_words[16];
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hex_to_512(data_hex, data_words);
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for (int w = 0; w < 16; w++) dut->data_i[w] = data_words[w];
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// Assert valid_i for one cycle
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dut->valid_i = 1;
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// posedge: DUT samples valid_i, starts keccak_core
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posedge(dut);
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cycle++;
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dut->valid_i = 0;
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// Wait for valid_o (keccak_core takes ~25 cycles)
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do {
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posedge(dut);
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cycle++;
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if (cycle > TIMEOUT_CYCLES) {
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std::cerr << "ERROR: Timeout waiting for valid_o (vec " << vec_count << ")" << std::endl;
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goto done;
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}
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} while (!dut->valid_o);
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// Read hash_o and print
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uint32_t hash_words[16];
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for (int w = 0; w < 16; w++) hash_words[w] = dut->hash_o[w];
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int out_bits = (mode_val == 0) ? 512 : 256;
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printf("RESULT: ");
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print_hex(hash_words, out_bits);
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// One more cycle for valid_o handshake
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posedge(dut);
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cycle++;
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vec_count++;
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}
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done:
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infile.close();
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delete dut;
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if (vec_count == 0) {
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std::cerr << "ERROR: No vectors processed" << std::endl;
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return 1;
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}
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return 0;
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}
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