chore(tb): remove Verilator TBs + framework; parallelize XSIM runs
Verilator is no longer used (all verification is via Vivado XSIM). Remove: - 10 per-module tb_*.cpp Verilator testbenches - the entire test_framework/ Verilator harness (lib/, run_all.py, config.json, per-module test_plan.json/gen_vectors.py, golden vectors, reports) - stale specs: verilator-conventions.md, test_framework/structure.md (index.md updated to drop the Verilator entry) Parallelize run_tb.sh K x case execution (modules stay serial): - new run_xsim_jobs helper: compile+elaborate once (serial, populates the shared xsim.dir), then run each (K,case) xsim in its own private workdir with a COPY of xsim.dir (~1MB) so concurrent same-snapshot runs don't clobber each other's runtime logs. Each workdir symlinks the repo sync_rtl tree so the TB's repo-relative $readmemh vector paths resolve. - top/enc/dec runners refactored to build a (snapshot:K:case) spec list and hand it to run_xsim_jobs; ordered PASS/FAIL summary + per-job /tmp logs preserved. Bare './run_tb.sh top' now also takes the parallel path. Speedup (20 cores): top full sweep 2:11 -> 0:51 (~2.6x), ~320% CPU. Verified: top (11) / enc (9) / dec (9) all PASS; missing-vector runs still fail (file-not-found guard -> exit 1).
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// tb_sample_cbd.cpp - Verilator C++ testbench for sample_cbd_sync
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//
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// Reads test vectors from +VECTOR_FILE= plusarg.
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// Format: "SEED_HEX NONCE_HEX ETA"
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// SEED_HEX: 64 hex chars (256-bit seed, MSB-first)
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// NONCE_HEX: 2 hex chars (8-bit nonce)
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// ETA: "2" or "3" (decimal)
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//
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// Drives DUT with seed, nonce, eta. Waits for valid_o, collects 256
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// coefficients. Prints "RESULT: COEFF_HEX\n" for each coefficient.
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//
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// Clock: 10ns period. Reset: 2 cycles.
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// Timeout: 500000 cycles.
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <sstream>
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#include <cstdlib>
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#include <cstring>
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#include <cstdint>
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#include "Vsample_cbd_sync.h"
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#include "verilated.h"
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#define CLK_PERIOD_NS 10.0
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#define TIMEOUT_CYCLES 500000
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static vluint64_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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// Toggle clock: both edges + eval (one full cycle)
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static void posedge(Vsample_cbd_sync* dut) {
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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}
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static int hex_char_to_nibble(char c) {
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if (c >= '0' && c <= '9') return c - '0';
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if (c >= 'A' && c <= 'F') return c - 'A' + 10;
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if (c >= 'a' && c <= 'f') return c - 'a' + 10;
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return 0;
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}
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// Parse hex string (MSB-first) into 8 x 32-bit words for 256-bit seed.
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// Word 0 = bits[31:0], word 7 = bits[255:224].
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// Hex string: leftmost char = most significant nibble (bits 255:252).
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static void hex_to_256(const std::string& hex, uint32_t data_words[8]) {
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for (int w = 0; w < 8; w++) data_words[w] = 0;
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int len = (int)hex.length();
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int nibble_idx = 0;
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for (int i = len - 1; i >= 0; i--) {
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char c = hex[i];
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if (c == ' ' || c == '\t') continue;
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int nib = hex_char_to_nibble(c);
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int word_idx = nibble_idx / 8;
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int shift = (nibble_idx % 8) * 4;
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if (word_idx < 8) {
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data_words[word_idx] |= ((uint32_t)nib << shift);
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}
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nibble_idx++;
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}
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}
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// Parse 2-char hex string into an 8-bit value.
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// "FF" → 0xFF, "0A" → 0x0A.
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static uint8_t hex_to_8(const std::string& hex) {
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int val = 0;
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for (size_t i = 0; i < hex.length(); i++) {
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val = (val << 4) | hex_char_to_nibble(hex[i]);
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}
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return (uint8_t)(val & 0xFF);
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv);
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// Parse +VECTOR_FILE= plusarg
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const char* vector_file = NULL;
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for (int i = 1; i < argc; i++) {
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std::string arg(argv[i]);
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if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
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vector_file = argv[i] + 13;
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}
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}
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if (!vector_file) {
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std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
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return 1;
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}
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std::ifstream infile(vector_file);
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if (!infile.is_open()) {
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std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
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return 1;
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}
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// Instantiate DUT
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Vsample_cbd_sync* dut = new Vsample_cbd_sync;
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// Initialize
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dut->clk = 0;
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dut->rst_n = 0;
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for (int w = 0; w < 8; w++) dut->seed_i[w] = 0;
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dut->nonce_i = 0;
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dut->eta_i = 0;
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dut->valid_i = 0;
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dut->ready_i = 0;
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// Reset: 2 full cycles
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for (int i = 0; i < 2; i++) posedge(dut);
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dut->rst_n = 1;
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// Consumer always ready
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dut->ready_i = 1;
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std::string line;
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vluint64_t cycle = 0;
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int vec_count = 0;
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int total_coeff_count = 0;
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while (std::getline(infile, line)) {
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if (line.empty() || line[0] == '#') continue;
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// Parse: SEED_HEX NONCE_HEX ETA
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std::istringstream iss(line);
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std::string seed_hex, nonce_hex;
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int eta_val;
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if (!(iss >> seed_hex >> nonce_hex >> eta_val)) continue;
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if (seed_hex.length() < 64) continue;
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// Set seed_i (256 bits)
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uint32_t seed_words[8];
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hex_to_256(seed_hex, seed_words);
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for (int w = 0; w < 8; w++) dut->seed_i[w] = seed_words[w];
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// Set nonce_i (8 bits)
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dut->nonce_i = hex_to_8(nonce_hex);
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// Set eta_i (2'd2 or 2'd3)
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dut->eta_i = (eta_val == 3) ? 3 : 2;
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// Assert valid_i for one cycle
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dut->valid_i = 1;
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posedge(dut);
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cycle++;
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dut->valid_i = 0;
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// Wait for 256 coefficients
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int coeffs_collected = 0;
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bool timed_out = false;
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while (coeffs_collected < 256) {
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posedge(dut);
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cycle++;
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if (cycle > TIMEOUT_CYCLES) {
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std::cerr << "ERROR: Timeout waiting for coeffs (vec "
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<< vec_count << ", got " << coeffs_collected
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<< "/256)" << std::endl;
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timed_out = true;
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break;
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}
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if (dut->valid_o && dut->ready_i) {
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// Read 12-bit coefficient and print
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uint32_t coeff = dut->coeff_o & 0xFFF;
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printf("RESULT: %03X\n", coeff);
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coeffs_collected++;
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total_coeff_count++;
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}
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}
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if (timed_out) {
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goto done;
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}
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// Wait for DUT to return to IDLE before next vector
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int wait_cycles = 0;
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while (!dut->ready_o && wait_cycles < 100) {
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posedge(dut);
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cycle++;
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wait_cycles++;
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}
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vec_count++;
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}
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done:
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infile.close();
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delete dut;
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if (vec_count == 0) {
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std::cerr << "ERROR: No vectors processed" << std::endl;
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return 1;
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}
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return 0;
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}
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