chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

Verilator is no longer used (all verification is via Vivado XSIM). Remove:
- 10 per-module tb_*.cpp Verilator testbenches
- the entire test_framework/ Verilator harness (lib/, run_all.py, config.json,
  per-module test_plan.json/gen_vectors.py, golden vectors, reports)
- stale specs: verilator-conventions.md, test_framework/structure.md
  (index.md updated to drop the Verilator entry)

Parallelize run_tb.sh K x case execution (modules stay serial):
- new run_xsim_jobs helper: compile+elaborate once (serial, populates the
  shared xsim.dir), then run each (K,case) xsim in its own private workdir
  with a COPY of xsim.dir (~1MB) so concurrent same-snapshot runs don't clobber
  each other's runtime logs. Each workdir symlinks the repo sync_rtl tree so
  the TB's repo-relative $readmemh vector paths resolve.
- top/enc/dec runners refactored to build a (snapshot:K:case) spec list and
  hand it to run_xsim_jobs; ordered PASS/FAIL summary + per-job /tmp logs
  preserved. Bare './run_tb.sh top' now also takes the parallel path.

Speedup (20 cores): top full sweep 2:11 -> 0:51 (~2.6x), ~320% CPU.
Verified: top (11) / enc (9) / dec (9) all PASS; missing-vector runs still
fail (file-not-found guard -> exit 1).

sync_rtl/rng/TB/tb_rng.cpp

@@ -1,94 +0,0 @@
-// tb_rng.cpp - Verilator C++ testbench for rng_sync
-//
-// Drives valid_i pulses and prints 256-bit LFSR output values.
-// Reads a hex input file to determine how many vectors to generate
-// (one line per vector, content ignored).
-// Prints "RESULT: <64-char hex>" for each output.
-//
-// Clock: 10ns period. Reset: 2 cycles low.
-// Timeout: 100,000 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <cstdio>
-#include "Vrng_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS 10.0
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13;
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Count non-empty, non-comment lines to determine vector count
-    int num_vectors = 0;
-    std::string line;
-    while (std::getline(infile, line)) {
-        if (!line.empty() && line[0] != '#')
-            num_vectors++;
-    }
-    infile.close();
-
-    // Instantiate DUT
-    Vrng_sync* dut = new Vrng_sync;
-
-    // Initialize
-    dut->clk     = 0;
-    dut->rst_n   = 0;
-    dut->valid_i = 0;
-    dut->ready_i = 0;
-
-    // Reset: 2 cycles low
-    for (int i = 0; i < 4; i++) {
-        dut->clk = 1; main_time += 5; dut->eval();
-        dut->clk = 0; main_time += 5; dut->eval();
-    }
-    dut->rst_n   = 1;
-    dut->ready_i = 1;
-
-    // Generate vectors
-    for (int n = 0; n < num_vectors; n++) {
-        // Drive valid_i and posedge → LFSR advances, valid_o→1
-        dut->valid_i = 1;
-        dut->clk = 1; main_time += 5; dut->eval();
-        dut->clk = 0; main_time += 5; dut->eval();
-        dut->valid_i = 0;
-
-        // Posedge to consume → valid_o→0
-        dut->clk = 1; main_time += 5; dut->eval();
-        // Print 256-bit result (8 × 32-bit words, MSB first)
-        printf("RESULT: %08X%08X%08X%08X%08X%08X%08X%08X\n",
-               dut->data_o[7], dut->data_o[6], dut->data_o[5], dut->data_o[4],
-               dut->data_o[3], dut->data_o[2], dut->data_o[1], dut->data_o[0]);
-        dut->clk = 0; main_time += 5; dut->eval();
-    }
-
-    delete dut;
-    return 0;
-}