chore(tb): remove Verilator TBs + framework; parallelize XSIM runs
Verilator is no longer used (all verification is via Vivado XSIM). Remove: - 10 per-module tb_*.cpp Verilator testbenches - the entire test_framework/ Verilator harness (lib/, run_all.py, config.json, per-module test_plan.json/gen_vectors.py, golden vectors, reports) - stale specs: verilator-conventions.md, test_framework/structure.md (index.md updated to drop the Verilator entry) Parallelize run_tb.sh K x case execution (modules stay serial): - new run_xsim_jobs helper: compile+elaborate once (serial, populates the shared xsim.dir), then run each (K,case) xsim in its own private workdir with a COPY of xsim.dir (~1MB) so concurrent same-snapshot runs don't clobber each other's runtime logs. Each workdir symlinks the repo sync_rtl tree so the TB's repo-relative $readmemh vector paths resolve. - top/enc/dec runners refactored to build a (snapshot:K:case) spec list and hand it to run_xsim_jobs; ordered PASS/FAIL summary + per-job /tmp logs preserved. Bare './run_tb.sh top' now also takes the parallel path. Speedup (20 cores): top full sweep 2:11 -> 0:51 (~2.6x), ~320% CPU. Verified: top (11) / enc (9) / dec (9) all PASS; missing-vector runs still fail (file-not-found guard -> exit 1).
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// tb_poly_mul.cpp - Verilator C++ testbench for poly_mul_sync
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//
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// Reads test vectors from +VECTOR_FILE= plusarg.
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// Format: one line with 512 space-separated hex values:
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// A[0] A[1] ... A[255] B[0] B[1] ... B[255]
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// Each value is a 3-digit hex (12-bit).
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//
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// Drives DUT with 256 paired (A,B) coefficients, waits for valid_o,
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// then reads 256 output coefficients via valid/ready handshake.
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// Prints "RESULT: COEFF0 COEFF1 ... COEFF255\n" to stdout.
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//
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// Clock: 10ns period. Reset: 2 cycles.
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <sstream>
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#include <vector>
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#include <cstdlib>
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#include <cstring>
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#include <cstdint>
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#include "Vpoly_mul_sync.h"
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#include "verilated.h"
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#define CLK_PERIOD_NS 10.0
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#define TIMEOUT_CYCLES 500000
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static vluint64_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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// Toggle clock: both edges + eval (one full cycle)
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static void posedge(Vpoly_mul_sync* dut) {
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dut->clk = 1;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = 0;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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}
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static int hex_char_to_nibble(char c) {
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if (c >= '0' && c <= '9') return c - '0';
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if (c >= 'A' && c <= 'F') return c - 'A' + 10;
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if (c >= 'a' && c <= 'f') return c - 'a' + 10;
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return 0;
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}
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// Parse 3-char hex token to 12-bit value.
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static uint16_t hex3_to_val(const std::string& tok) {
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uint16_t val = 0;
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for (size_t i = 0; i < tok.length() && i < 3; i++) {
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val = (val << 4) | hex_char_to_nibble(tok[i]);
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}
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return val & 0xFFF;
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}
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// Format 12-bit value as 3-char hex.
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static std::string val_to_hex3(uint16_t val) {
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char buf[4];
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snprintf(buf, sizeof(buf), "%03X", val & 0xFFF);
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return std::string(buf);
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv);
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// Parse +VECTOR_FILE= plusarg
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const char* vector_file = NULL;
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for (int i = 1; i < argc; i++) {
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std::string arg(argv[i]);
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if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
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vector_file = argv[i] + 13;
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}
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}
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if (!vector_file) {
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std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
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return 1;
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}
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std::ifstream infile(vector_file);
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if (!infile.is_open()) {
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std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
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return 1;
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}
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// Instantiate DUT
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Vpoly_mul_sync* dut = new Vpoly_mul_sync;
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// Initialize
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dut->clk = 0;
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dut->rst_n = 0;
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dut->coeff_a_in = 0;
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dut->coeff_b_in = 0;
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dut->valid_i = 0;
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dut->ready_i = 0;
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// Reset: 2 full cycles
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for (int i = 0; i < 2; i++) posedge(dut);
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dut->rst_n = 1;
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std::string line;
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vluint64_t cycle = 0;
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int vec_count = 0;
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while (std::getline(infile, line)) {
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if (line.empty() || line[0] == '#') continue;
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// Parse: A[0] A[1] ... A[255] B[0] B[1] ... B[255]
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// Total: 512 hex values, one line
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std::istringstream iss(line);
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std::string tok;
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std::vector<uint16_t> input_coeffs(512);
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int coeff_idx = 0;
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while (iss >> tok && coeff_idx < 512) {
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input_coeffs[coeff_idx] = hex3_to_val(tok);
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coeff_idx++;
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}
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if (coeff_idx != 512) {
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std::cerr << "ERROR: Expected 512 coefficients, got " << coeff_idx
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<< " (vec " << vec_count << ")" << std::endl;
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continue;
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}
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// ---- Load 256 A+B pairs ----
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while (!dut->ready_o) {
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posedge(dut); cycle++;
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if (cycle > TIMEOUT_CYCLES) goto timeout_err;
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}
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for (int i = 0; i < 256; i++) {
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dut->coeff_a_in = input_coeffs[i];
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dut->coeff_b_in = input_coeffs[256 + i];
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dut->valid_i = 1;
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posedge(dut); cycle++;
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dut->valid_i = 0;
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if (cycle > TIMEOUT_CYCLES) goto timeout_err;
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}
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// ---- Wait for valid_o (DUT computing) ----
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dut->ready_i = 1;
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while (!dut->valid_o) {
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posedge(dut);
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cycle++;
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if (cycle > TIMEOUT_CYCLES) goto timeout_err;
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}
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// ---- Read 256 output coefficients ----
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printf("RESULT: ");
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for (int i = 0; i < 256; i++) {
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// Wait for valid_o to be asserted (data is valid NOW)
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while (!dut->valid_o) {
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posedge(dut);
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cycle++;
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if (cycle > TIMEOUT_CYCLES) goto timeout_err;
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}
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// Capture coefficient BEFORE consuming posedge
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uint16_t coeff_val = (uint16_t)(dut->coeff_out & 0xFFF);
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printf("%s%s", val_to_hex3(coeff_val).c_str(),
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(i < 255) ? " " : "");
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// Consume this coefficient: posedge with ready_i=1
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posedge(dut);
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cycle++;
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}
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printf("\n");
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vec_count++;
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}
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std::cout << "Processed " << vec_count << " vectors" << std::endl;
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infile.close();
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delete dut;
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return (vec_count > 0) ? 0 : 1;
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timeout_err:
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std::cerr << "ERROR: Timeout at cycle " << cycle
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<< " (vec " << vec_count << ")" << std::endl;
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infile.close();
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delete dut;
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return 1;
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}
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