chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

Verilator is no longer used (all verification is via Vivado XSIM). Remove:
- 10 per-module tb_*.cpp Verilator testbenches
- the entire test_framework/ Verilator harness (lib/, run_all.py, config.json,
  per-module test_plan.json/gen_vectors.py, golden vectors, reports)
- stale specs: verilator-conventions.md, test_framework/structure.md
  (index.md updated to drop the Verilator entry)

Parallelize run_tb.sh K x case execution (modules stay serial):
- new run_xsim_jobs helper: compile+elaborate once (serial, populates the
  shared xsim.dir), then run each (K,case) xsim in its own private workdir
  with a COPY of xsim.dir (~1MB) so concurrent same-snapshot runs don't clobber
  each other's runtime logs. Each workdir symlinks the repo sync_rtl tree so
  the TB's repo-relative $readmemh vector paths resolve.
- top/enc/dec runners refactored to build a (snapshot:K:case) spec list and
  hand it to run_xsim_jobs; ordered PASS/FAIL summary + per-job /tmp logs
  preserved. Bare './run_tb.sh top' now also takes the parallel path.

Speedup (20 cores): top full sweep 2:11 -> 0:51 (~2.6x), ~320% CPU.
Verified: top (11) / enc (9) / dec (9) all PASS; missing-vector runs still
fail (file-not-found guard -> exit 1).

sync_rtl/mod_add/TB/tb_mod_add.cpp

@@ -1,120 +0,0 @@
-// tb_mod_add.cpp - Verilator C++ testbench for mod_add_sync
-//
-// Reads test vectors from a hex file specified by +VECTOR_FILE= plusarg.
-// Each line: "AAA BBB" (two 12-bit hex operands).
-// Drives the DUT, waits for valid_o, writes "RESULT: CCC" to stdout.
-//
-// Clock: CLK_PERIOD ns period (from defines.vh).
-// Reset: 2 cycles low, then high.
-// Timeout: 100,000 cycles.
-
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <sstream>
-#include <cstdlib>
-#include "Vmod_add_sync.h"
-#include "verilated.h"
-
-#define CLK_PERIOD_NS    10.0
-#define TIMEOUT_CYCLES   100000
-#define Q                3329
-
-static vluint64_t main_time = 0;
-
-double sc_time_stamp() {
-    return main_time;
-}
-
-int main(int argc, char** argv) {
-    Verilated::commandArgs(argc, argv);
-
-    // Parse +VECTOR_FILE= plusarg
-    const char* vector_file = NULL;
-    for (int i = 1; i < argc; i++) {
-        std::string arg(argv[i]);
-        if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
-            vector_file = argv[i] + 13; // skip "+VECTOR_FILE="
-        }
-    }
-
-    if (!vector_file) {
-        std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
-        return 1;
-    }
-
-    std::ifstream infile(vector_file);
-    if (!infile.is_open()) {
-        std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
-        return 1;
-    }
-
-    // Instantiate DUT
-    Vmod_add_sync* dut = new Vmod_add_sync;
-
-    // Initialize
-    dut->clk    = 0;
-    dut->rst_n  = 0;
-    dut->a      = 0;
-    dut->b      = 0;
-    dut->valid_i = 0;
-    dut->ready_i = 0;
-
-    // Reset: 2 cycles low
-    for (int i = 0; i < 4; i++) {
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-    }
-    dut->rst_n = 1;
-
-    // Always ready to receive results
-    dut->ready_i = 1;
-
-    std::string line;
-    vluint64_t cycle = 0;
-    bool waiting_result = false;
-
-    while (std::getline(infile, line)) {
-        // Skip empty lines and comments
-        if (line.empty() || line[0] == '#') continue;
-
-        // Parse hex operands
-        std::istringstream iss(line);
-        unsigned int a_val, b_val;
-        if (!(iss >> std::hex >> a_val >> b_val)) continue;
-
-        dut->a       = a_val & 0xFFF;
-        dut->b       = b_val & 0xFFF;
-        dut->valid_i = 1;
-
-        // posedge: DUT samples valid_i, pipeline_reg captures data, valid_o→1
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        cycle++;
-        dut->valid_i = 0;
-
-        // posedge: pipeline_reg clears valid_o (ready_i=1), but result is
-        // available on sum port right now (combinational from data_r)
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        dut->clk = !dut->clk;
-        main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
-        dut->eval();
-        cycle++;
-
-        printf("RESULT: %03X\n", dut->sum & 0xFFF);
-    }
-
-    infile.close();
-    delete dut;
-    return 0;
-}